公开(公告)号：US09058987B2

公开(公告)日：2015-06-16

申请号：US14336407

申请日：2014-07-21

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02488 ,  H01L21/02513 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02642 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion.

Abstract translation: 电介质模板层沉积在衬底上。 通过使用图案化掩模层的各向异性蚀刻，在电介质模板层内形成线沟槽。 图案化掩模层可以是图案化的光致抗蚀剂层，或者通过其它图像转印方法形成的图案化的硬掩模层。 通过选择性稀土氧化物外延法，用外延稀土氧化物材料填充每个线沟槽的下部。 通过选择性半导体外延工艺，用外延半导体材料填充每个线沟槽的上部。 电介质模板层被凹入以形成介电材料层，该电介质材料层在散热片结构之间提供横向电隔离，其中每一个包括稀土氧化物翅片部分和半导体散热片部分的堆叠。

公开(公告)号：US20140213053A1

公开(公告)日：2014-07-31

申请号：US13749830

申请日：2013-01-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karen A. Nummy ,  Ravi M. Todi

IPC: H01L21/02

CPC classification number: H01L21/743 ,  H01L29/945

Abstract: A method of forming a contact on a semiconductor device is disclosed. The method includes: forming a mask on the semiconductor device, the mask exposing at least one contact node disposed within a trench in a substrate of the semiconductor device; performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the exposed contact node within the trench; removing a set of node films disposed above the exposed contact node and on the sides of the trench; and forming a contact region within the trench above the exposed contact node, the contact region contacting the substrate.

Abstract translation: 公开了一种在半导体器件上形成接触的方法。 所述方法包括：在所述半导体器件上形成掩模，所述掩模暴露设置在所述半导体器件的衬底中的沟槽内的至少一个接触节点; 在所述半导体器件上执行第一衬底接触蚀刻，所述第一衬底接触蚀刻凹陷所述沟槽内的所述暴露的接触节点; 去除设置在暴露的接触节点之上和沟槽的侧面上的一组节点膜; 以及在所述暴露的接触节点之上的所述沟槽内形成接触区域，所述接触区域接触所述衬底。

公开(公告)号：US20130183806A1

公开(公告)日：2013-07-18

申请号：US13788406

申请日：2013-03-07

Applicant: International Business Machines Corporation

Inventor： Roger A. Booth ,  Kangguo Cheng ,  Joseph Ervin ,  David M. Fried ,  Byeong Y. Kim ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L29/92

CPC classification number: H01L29/92 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1203

Abstract: In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.

Abstract translation: 在垂直动态存储单元中，通过在绝缘体材料上的横向外延生长（其补充电容器电介质完全围绕存储节点，除了接触连接结构，优选地，存储晶体管的沟道）为存取晶体管的沟道提供改善的质量的单晶半导体材料 的金属，从存取晶体管到存储节点电极），并蚀刻掉包括最可能发生晶格位错的位置的横向外延生长的区域; 这两个特征用于减少或避免从存储节点泄漏电荷。 可以在蚀刻区域中提供隔离结构，使得提供用于连接到存储单元阵列的各个部分的空间。