公开(公告)号：US10818668B2

公开(公告)日：2020-10-27

申请号：US15825961

申请日：2017-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/74 ,  H01L21/762 ,  H01L29/66 ,  H01L27/12 ,  H01L29/06 ,  H01L27/06

Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

公开(公告)号：US20150279843A1

公开(公告)日：2015-10-01

申请号：US14736695

申请日：2015-06-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/108

CPC classification number: H01L27/10823 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66181

Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

Abstract translation: 提供了一种存储器件，其包括绝缘体上半导体（SOI）衬底，其包括位于掩埋介电层顶部的第一半导体层，其中所述掩埋介电层覆盖在第二半导体层上。 电容器存在于沟槽中，其中沟槽从第一半导体层的上表面延伸穿过埋入介质层并延伸到第二半导体层。 保护性氧化物存在于位于第一半导体层附近的空隙中，并且传导晶体管存在于与电容器电连通的绝缘体上半导体衬底上。

公开(公告)号：US09087928B2

公开(公告)日：2015-07-21

申请号：US13788406

申请日：2013-03-07

Applicant: International Business Machines Corporation

Inventor： Roger A. Booth ,  Kangguo Cheng ,  Joseph Ervin ,  David M. Fried ,  Byeong Y. Kim ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L21/20 ,  H01L29/92 ,  H01L27/108 ,  H01L27/12

CPC classification number: H01L29/92 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1203

Abstract: In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.

Abstract translation: 在垂直动态存储单元中，通过在绝缘体材料上的横向外延生长（其补充电容器电介质完全围绕存储节点，除了接触连接结构，优选地，存储晶体管的沟道）为存取晶体管的沟道提供改善的质量的单晶半导体材料 的金属，从存取晶体管到存储节点电极），并蚀刻掉包括最可能发生晶格位错的位置的横向外延生长的区域; 这两个特征用于减少或避免从存储节点泄漏电荷。 可以在蚀刻区域中提供隔离结构，使得提供用于连接到存储单元阵列的各个部分的空间。

公开(公告)号：US20150037939A1

公开(公告)日：2015-02-05

申请号：US14336407

申请日：2014-07-21

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L21/02488 ,  H01L21/02513 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02642 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion.

Abstract translation: 电介质模板层沉积在衬底上。 通过使用图案化掩模层的各向异性蚀刻，在电介质模板层内形成线沟槽。 图案化掩模层可以是图案化的光致抗蚀剂层，或者通过其它图像转印方法形成的图案化的硬掩模层。 通过选择性稀土氧化物外延法，用外延稀土氧化物材料填充每个线沟槽的下部。 通过选择性半导体外延工艺，用外延半导体材料填充每个线沟槽的上部。 电介质模板层被凹入以形成介电材料层，该电介质材料层在散热片结构之间提供横向电隔离，其中每一个包括稀土氧化物翅片部分和半导体散热片部分的堆叠。

公开(公告)号：US08936992B2

公开(公告)日：2015-01-20

申请号：US14146198

申请日：2014-01-02

Applicant: International Business Machines Corporation

Inventor： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L21/20 ,  H01L21/70 ,  H01L27/108 ,  H01L27/12 ,  H01L29/94

CPC classification number: H01L27/1087 ,  H01L27/10829 ,  H01L27/1203 ,  H01L29/945

Abstract: Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.

Abstract translation: 在绝缘体上半导体（SOI）衬底中形成具有不同宽度的两个沟槽。 在沟槽中形成不透氧层和填充材料层。 从第一沟槽内去除填充材料层和不透氧层。 执行热氧化以将第一沟槽的侧壁下的半导体材料转换成上部热氧化物部分和下部热氧化物部分，而在第二沟槽的侧壁上的剩余的不透氧层防止半导体材料的氧化。 在第二沟槽的侧壁上形成节点电介质之后，沉积导电材料以填充沟槽，从而分别形成导电沟槽填充部分和内部电极。 上部和下部热氧化物部分用作电绝缘两个器件区域的介电材料部分的部件。

公开(公告)号：US08836003B2

公开(公告)日：2014-09-16

申请号：US14090033

申请日：2013-11-26

Applicant: International Business Machines Corporation

Inventor： Joseph Ervin ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/94 ,  H01L27/12 ,  H01L21/84 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer including a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer including a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI.

Abstract translation: 公开了深沟槽电容器结构和制造方法。 该方法包括在包括衬底，掩埋氧化物层（BOX）和硅（SOI））膜的晶片中形成深沟槽结构。 该结构包括晶片，其包括衬底，埋入绝缘体层和在整个层中具有单晶结构的绝缘体上硅层（SOI）层。 该结构还包括基板中的第一板和与第一板直接接触的绝缘体层。 掺杂多晶硅与绝缘体层直接接触，并且与SOI的单晶结构直接接触。

公开(公告)号：US08754461B2

公开(公告)日：2014-06-17

申请号：US13905204

申请日：2013-05-30

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L29/94

CPC classification number: H01L29/0649 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

Abstract: A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.

Abstract translation: 在深沟槽中形成改进的间隔隔离的方法，包括将形成在绝缘体上硅（SOI）衬底中的深沟槽内沉积的节点电介质，第一导电层和第二导电层凹入到低于 SOI衬底的掩埋氧化物层，并且在深沟槽中形成具有底表面的开口。 还包括沿深沟槽的侧壁和开口的底表面沉积间隔物，以及从开口的底表面移除隔离物。 在一个方向上以一定角度进行离子注入和离子轰击中的至少一个进入间隔物的上部。 从深沟槽的侧壁上去除隔离物的上部。 在开口内沉积第三导电层。

公开(公告)号：US20130328161A1

公开(公告)日：2013-12-12

申请号：US13905204

申请日：2013-05-30

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

Abstract: A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.

公开(公告)号：US20130193562A1

公开(公告)日：2013-08-01

申请号：US13827463

申请日：2013-03-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ravi M. Todi ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

IPC: H01L29/02

CPC classification number: H01L29/02 ,  H01L21/76254

Abstract: A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.

Abstract translation: 提供了包括具有特征的半导体氧化物层的半导体结构。 具有特征的半导体氧化物层位于有源半导体层和手柄基板之间。 半导体结构包括有源半导体层的平坦化顶表面，使得半导体氧化物层位于平坦化的顶表面之下。 半导体氧化物层内的特征与有源半导体层的表面配合。

公开(公告)号：US20130134527A1

公开(公告)日：2013-05-30

申请号：US13748942

申请日：2013-01-24

Applicant: International Business Machines Corporation

Inventor： Chengwen Pei ,  Roger Allen Booth ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

IPC: H01L29/49

CPC classification number: H01L29/49 ,  H01L21/743 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78612

Abstract: A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.

Abstract translation: 公开了一种在晶体管上制造体接触的结构和方法。 该方法包括在处理晶片上形成具有晶体管的半导体结构。 然后将结构反转，并移除手柄晶片。 然后在倒置位置的晶体管上形成硅化物体接触。 身体接触可以连接到相邻的通孔，以将身体接触连接到其他结构或水平以形成集成电路。