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    SELF-ALIGNED LATERALLY EXTENDED STRAP FOR A DYNAMIC RANDOM ACCESS MEMORY CELL
    2.
    发明申请
    SELF-ALIGNED LATERALLY EXTENDED STRAP FOR A DYNAMIC RANDOM ACCESS MEMORY CELL 有权
    用于动态随机访问存储器单元的自对准的横向扩展条带

    公开(公告)号：US20150162336A1

    公开(公告)日：2015-06-11

    申请号：US14098639

    申请日：2013-12-06

    申请人： International Business Machines Corporation

    发明人： Byeong Y. Kim ,  Dan M. Mocuta

    IPC分类号： H01L27/108 ,  H01L29/66 ,  H01L21/321 ,  H01L21/306 ,  H01L21/308

    CPC分类号： H01L27/10832 ,  H01L21/3086 ,  H01L27/10826 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/6656 ,  H01L29/785

    摘要： A self-aligned strap structure can be formed by forming trench capacitors and overlying trench top conductive material portions. End portions of fin mask structures overlie portions of the trench top conductive material portions. A dielectric spacer is formed around each end portions of the fin mask structure to cover additional areas of the trench top conductive material portions. An anisotropic etch is performed to recess portions of the trench top conductive material portions that are not covered by the fin mask structures or dielectric spacers. Conductive strap structures that are self-aligned to end portions of semiconductor fins are formed simultaneously with formation of the semiconductor fins. Access fin field effect transistors can be subsequently formed.

    摘要翻译： 可以通过形成沟槽电容器和覆盖沟槽顶部导电材料部分来形成自对准带结构。 翅片掩模结构的端部覆盖在沟槽顶部导电材料部分的部分上。 围绕翅片掩模结构的每个端部形成介电隔离件以覆盖沟槽顶部导电材料部分的附加区域。 执行各向异性蚀刻以凹陷未被翅片掩模结构或电介质间隔物覆盖的沟槽顶部导电材料部分的部分。 与半导体翅片的端部自对准的导电带结构同时形成半导体翅片。 可以随后形成接入鳍场效应晶体管。

    Embedded DRAM memory cell with additional patterning layer for improved strap formation
    3.
    发明授权
    Embedded DRAM memory cell with additional patterning layer for improved strap formation 有权
    具有附加图形层的嵌入式DRAM存储单元，用于改善表带形成

    公开(公告)号：US08772850B2

    公开(公告)日：2014-07-08

    申请号：US13865306

    申请日：2013-04-18

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Byeong Y. Kim ,  Munir D. Naeem

    IPC分类号： H01L27/108

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10867 ,  H01L27/1087 ,  H01L29/66181

    摘要： A method of forming a memory cell including forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed.

    摘要翻译： 一种形成包括在层状半导体结构中形成沟槽的存储单元的方法，每个沟槽具有与沟槽之间的分层半导体结构的一部分相邻的内侧壁和与内侧壁相对的外侧壁。 沟槽填充有多晶硅，并且图案化层形成在层状半导体结构之上。 然后通过图案化图案将开口图案化，开口暴露沟槽之间的分层半导体结构的部分，并且仅沿着每个沟槽的内侧壁的多晶硅的垂直部分。 然后蚀刻层状半导体结构。 图案化层防止沿着每个沟槽的外侧壁的多晶硅的第二垂直部分被去除。

    High Density Memory Cells Using Lateral Epitaxy
    6.
    发明申请
    High Density Memory Cells Using Lateral Epitaxy 有权
    高密度记忆细胞使用侧向外延

    公开(公告)号：US20130183806A1

    公开(公告)日：2013-07-18

    申请号：US13788406

    申请日：2013-03-07

    申请人： International Business Machines Corporation

    发明人： Roger A. Booth ,  Kangguo Cheng ,  Joseph Ervin ,  David M. Fried ,  Byeong Y. Kim ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L29/92

    CPC分类号： H01L29/92 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1203

    摘要： In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.

    摘要翻译： 在垂直动态存储单元中，通过在绝缘体材料上的横向外延生长（其补充电容器电介质完全围绕存储节点，除了接触连接结构，优选地，存储晶体管的沟道）为存取晶体管的沟道提供改善的质量的单晶半导体材料 的金属，从存取晶体管到存储节点电极），并蚀刻掉包括最可能发生晶格位错的位置的横向外延生长的区域; 这两个特征用于减少或避免从存储节点泄漏电荷。 可以在蚀刻区域中提供隔离结构，使得提供用于连接到存储单元阵列的各个部分的空间。

    Shallow trench isolation structure having a nitride plug
    10.
    发明授权
    Shallow trench isolation structure having a nitride plug 有权
    具有氮化物塞的浅沟槽隔离结构

    公开(公告)号：US09443929B2

    公开(公告)日：2016-09-13

    申请号：US14532230

    申请日：2014-11-04

    申请人： International Business Machines Corporation

    发明人： Byeong Y. Kim ,  Shreesh Narasimha

    IPC分类号： H01L29/06 ,  H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762

    CPC分类号： H01L29/0649 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203

    摘要： A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates.

    摘要翻译： 一种用于形成具有一个或多个氧化物层和氮化物塞的浅沟槽隔离（STI）结构的半导体结构和方法。 具体地，该结构和方法包括在衬底中形成一个或多个沟槽。 STI结构形成为具有一个或多个氧化物层和氮化物塞，其中STI结构形成在一个或多个沟槽中的至少一个沟槽上并与其相邻。 一个或多个栅极形成在衬底上并且彼此间隔开一定距离。 介电层形成在衬底上，并且邻近衬底，STI结构和一个或多个栅极。