公开(公告)号：US08158481B2

公开(公告)日：2012-04-17

申请号：US12683535

申请日：2010-01-07

申请人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/8234

CPC分类号： H01L21/28079 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/6659

摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

摘要翻译： 制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。 第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。 平坦化层位于第二栅极材料层上。 平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。 也可以在第一栅极叠层上形成蚀刻停止层。 所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

公开(公告)号：US20110042687A1

公开(公告)日：2011-02-24

申请号：US12546034

申请日：2009-08-24

申请人： Jack O. Chu ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  Chun-yung Sung

发明人： Jack O. Chu ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  Chun-yung Sung

IPC分类号： H01L29/24 ,  H01L21/311 ,  H01L21/20 ,  B32B9/00

CPC分类号： H01L29/1606 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/184 ,  C01B2204/04 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/02667 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/161 ,  Y10T428/265

摘要： A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.

摘要翻译： 半导体 - 碳合金层形成在半导体衬底的表面上，半导体衬底的表面可以是诸如硅衬底的市售半导体衬底。 半导体 - 碳合金层在高温退火期间被转化为至少一个石墨烯层，在此期间半导体 - 碳合金层表面上的半导体材料对碳原子有选择性的蒸发。 随着半导体原子被选择性地去除并且半导体 - 碳合金层的表面上的碳浓度增加，半导体 - 碳合金层顶层中剩余的碳原子聚结形成具有至少一个石墨烯单层的石墨烯层 。 因此，可以在直径为200mm或300mm的市售半导体衬底上提供石墨烯层。

公开(公告)号：US20070278586A1

公开(公告)日：2007-12-06

申请号：US11444011

申请日：2006-05-31

申请人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L29/94

CPC分类号： H01L21/28079 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/6659

摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

摘要翻译： 制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。 第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。 平坦化层位于第二栅极材料层上。 平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。 也可以在第一栅极叠层上形成蚀刻停止层。 所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。