公开(公告)号：US07943460B2

公开(公告)日：2011-05-17

申请号：US12426457

申请日：2009-04-20

申请人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

发明人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/78

摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.

摘要翻译： 提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。 此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。 然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。

公开(公告)号：US07671421B2

公开(公告)日：2010-03-02

申请号：US11444011

申请日：2006-05-31

申请人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/00

CPC分类号： H01L21/28079 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/6659

摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

摘要翻译： 制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。 第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。 平坦化层位于第二栅极材料层上。 平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。 也可以在第一栅极叠层上形成蚀刻停止层。 所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

公开(公告)号：US06893979B2

公开(公告)日：2005-05-17

申请号：US09809663

申请日：2001-03-15

申请人： Mukesh V. Khare ,  Christopher P. D'Emic ,  Thomas T. Hwang ,  Paul C. Jamison ,  James J. Quinlivan ,  Beth A. Ward

发明人： Mukesh V. Khare ,  Christopher P. D'Emic ,  Thomas T. Hwang ,  Paul C. Jamison ,  James J. Quinlivan ,  Beth A. Ward

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L29/51 ,  H01L29/78 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L29/518 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/3144

摘要： A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.

摘要翻译： 一种用于形成用于集成电路器件的栅极电介质的方法。 在本发明的示例性实施例中，该方法包括在基底材料上形成初始氧氮化物层，该氮氧化物层具有初始物理厚度。 然后对初始氧氮化物层进行等离子体氮化处理，等离子体氮化导致最终的氧氮化物层具有最终的物理厚度。

公开(公告)号：US06635517B2

公开(公告)日：2003-10-21

申请号：US09924014

申请日：2001-08-07

申请人： Tze-Chiang Chen ,  Thomas T. Hwang ,  Mukesh V. Khare ,  Effendi Leobandung ,  Anda C. Mocuta ,  Paul A. Ronsheim ,  Ghavam G. Shahidi

发明人： Tze-Chiang Chen ,  Thomas T. Hwang ,  Mukesh V. Khare ,  Effendi Leobandung ,  Anda C. Mocuta ,  Paul A. Ronsheim ,  Ghavam G. Shahidi

IPC分类号： H01L21335

CPC分类号： H01L29/66772 ,  H01L21/26506 ,  H01L21/3226 ,  H01L29/78654

摘要： A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate stack region being formed on a top Si-containing layer of an SOI substrate; implanting gettering species into the top Si-containing layer not protected by the disposable spacer and patterned gate stack region; and removing the disposable spacer and annealing the implanted gettering species so as to convert said species into a gettering region.

摘要翻译： 提供了在SOI衬底内形成自对准吸气区域的方法。 具体地，本发明的方法包括以下步骤：在图案化的栅极堆叠区域的每个垂直侧壁上形成一次性间隔物，所述图案化栅极堆叠区域形成在SOI衬底的顶部含Si层上; 将吸气物质注入到不被一次性间隔物和图案化的栅堆叠区域保护的顶部含Si层中; 以及去除一次性间隔物并退火植入的吸气物质，以便将所述物种转化成吸气区域。

公开(公告)号：US06569781B1

公开(公告)日：2003-05-27

申请号：US10054078

申请日：2002-01-22

申请人： Omer H. Dokumaci ,  Richard D. Kaplan ,  Mukesh V. Khare ,  Suryanarayan G. Hegde

发明人： Omer H. Dokumaci ,  Richard D. Kaplan ,  Mukesh V. Khare ,  Suryanarayan G. Hegde

IPC分类号： H01L21265

CPC分类号： H01L21/28211 ,  H01L21/26506 ,  H01L21/2822 ,  H01L21/28238 ,  H01L29/518

摘要： A method for forming an oxide layer on a silicon substrate includes forming a sacrificial oxide layer on the silicon substrate, implanting nitrogen into the silicon substrate, annealing the silicon substrate having implanted nitrogen, removing the sacrificial oxide layer from the silicon substrate, and forming an oxide layer on the silicon substrate. The dose of nitrogen implanted into silicon is preferably higher than 1e14 cm31 2. The annealing process is preferably performed at temperatures in a range from about 550° C. to about 1000° C. and for a time period between about 1 second and about 2 hours.

摘要翻译： 在硅衬底上形成氧化物层的方法包括在硅衬底上形成牺牲氧化物层，将氮注入到硅衬底中，退火具有注入氮的硅衬底，从硅衬底去除牺牲氧化层， 硅衬底上的氧化物层。 植入硅中的氮的剂量优选高于1e14cm31 2.退火过程优选在约550℃至约1000℃的温度下进行约1秒至约2秒的时间 小时。

公开(公告)号：US20120142181A1

公开(公告)日：2012-06-07

申请号：US13369707

申请日：2012-02-09

申请人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/28

CPC分类号： H01L21/28079 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/6659

摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

摘要翻译： 制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。 第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。 平坦化层位于第二栅极材料层上。 平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。 也可以在第一栅极叠层上形成蚀刻停止层。 所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

公开(公告)号：US08158481B2

公开(公告)日：2012-04-17

申请号：US12683535

申请日：2010-01-07

申请人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/8234

CPC分类号： H01L21/28079 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/6659

摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

摘要翻译： 制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。 第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。 平坦化层位于第二栅极材料层上。 平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。 也可以在第一栅极叠层上形成蚀刻停止层。 所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

公开(公告)号：US20110156158A1

公开(公告)日：2011-06-30

申请号：US13048170

申请日：2011-03-15

申请人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

发明人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/78

摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.

摘要翻译： 提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。 此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。 然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。

公开(公告)号：US20100264495A1

公开(公告)日：2010-10-21

申请号：US12426457

申请日：2009-04-20

申请人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

发明人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/78

摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.

摘要翻译： 提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。 此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。 然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。

公开(公告)号：US6096580A

公开(公告)日：2000-08-01

申请号：US405331

申请日：1999-09-24

申请人： S. Sundar Kumar Iyer ,  Liang-Kai Han ,  Robert Hannon ,  Subramanian S. Iyer ,  Mukesh V. Khare

发明人： S. Sundar Kumar Iyer ,  Liang-Kai Han ,  Robert Hannon ,  Subramanian S. Iyer ,  Mukesh V. Khare

IPC分类号： H01L23/525 ,  H01L21/82

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： A low programming voltage anti-fuse formed by a MOSFET (or MOS) or by a deep trench (DT) capacitor structure is described. Lowering the programming voltage is achieved by implanting a dose of heavy ions, such as indium, into the dielectric directly on the substrate or indirectly through a layer of polysilicon. The programming voltage can also be lowered on the MOSFET/MOS capacitor anti-fuse by accentuating the corners of active areas and gate areas of the device with suitable layout masks during processing. Silicon active area corner rounding steps should also be avoided in the fabrication of the anti-fuse to reduce the programming voltage. In the DT capacitor, lowering the programming voltage may be achieved by implanting the node dielectric of the DT anti-fuse with heavy ions either directly or through a conformal layer of polysilicon deposited on it or after the first amorphous silicon recess step during the fabrication of the DT capacitor.

摘要翻译： 描述了由MOSFET（或MOS）或深沟槽（DT）电容器结构形成的低编程电压反熔丝。 降低编程电压可以通过将一定剂量的重离子（如铟）直接注入到基底上的电介质或间接通过多晶硅层来实现。 通过在处理期间通过适当的布局掩模强调器件的有源区域和栅极区域的角，也可以在MOSFET / MOS电容器反熔丝上降低编程电压。 在制造抗熔丝的同时，也应避免硅有源区四舍五入步骤，以减少编程电压。 在DT电容器中，降低编程电压可以通过直接或通过沉积在其上的多晶硅的保形层或在第一非晶硅凹槽步骤之后的重离子注入DT反熔丝的节点电介质来实现， DT电容器。