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31.发明申请Method, system, and program product for computing a yield gradient from statistical timing 有权用于从统计时序计算产量梯度的方法，系统和程序产品公开(公告)号：US20070234252A1
公开(公告)日：2007-10-04
申请号：US11358622
申请日：2006-02-21
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F17/5031 , G06F17/504 , G06F2217/10 , G06F2217/12 , Y02P90/265
摘要： The invention provides a method, system, and program product for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit. A first aspect of the invention provides a method for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit, the method comprising: conducting a statistical timing analysis; expressing a statistical circuit delay in terms of a delay of the edge; and computing a gradient of the statistical circuit delay with respect to parameters of the delay of the edge.
摘要翻译： 本发明提供了一种方法，系统和程序产品，用于相对于电路的时序图的边沿的延迟的参数来确定集成电路的参数收益率的梯度。 本发明的第一方面提供了一种用于根据电路的时序图的边沿的延迟的参数来确定集成电路的参数收益率的梯度的方法，所述方法包括：进行统计时序分析; 根据边缘的延迟表示统计电路延迟; 以及计算相对于边缘的延迟的参数的统计电路延迟的梯度。
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32.发明申请公开(公告)号：US20130283223A1
公开(公告)日：2013-10-24
申请号：US13454795
申请日：2012-04-24
申请人： Bhavna Agrawal , David S. Kung , Jinjun Xiong , Vladimir Zolotov
发明人： Bhavna Agrawal , David S. Kung , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G01R31/31725 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for variation enabling statistical testing using deterministic multi-corner timing analysis. One embodiment of a method for obtaining statistical timing data for an integrated circuit chip includes obtaining deterministic multi-corner timing data for the integrated circuit chip and constructing the statistical timing data from the deterministic multi-corner timing data.
摘要翻译： 在一个实施例中，本发明是用于使用确定性多角时间分析进行统计测试的变化的方法和装置。 用于获得用于集成电路芯片的统计定时数据的方法的一个实施例包括获得用于集成电路芯片的确定性多角定时数据并从确定性多角定时数据构建统计定时数据。
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33.发明申请DISPOSITION OF INTEGRATED CIRCUITS USING PERFORMANCE SORT RING OSCILLATOR AND PERFORMANCE PATH TESTING 有权使用性能排序振荡器和性能路径测试处理集成电路公开(公告)号：US20130125076A1
公开(公告)日：2013-05-16
申请号：US13294220
申请日：2011-11-11
IPC分类号： G06F17/50
CPC分类号： G01R31/3016 , G01R31/31725
摘要： A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.
摘要翻译： 一种配置集成电路芯片的方法和系统。 该方法包括对具有一个或多个时钟域的集成电路芯片执行性能路径测试，该性能路径测试基于将测试图案应用于集成电路芯片的不同时钟频率的选择的可敏化数据路径; 并且基于性能路径测试的结果来布置集成电路芯片。
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公开(公告)号：US20130014075A1
公开(公告)日：2013-01-10
申请号：US13617749
申请日：2012-09-14
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/31725 , G06F17/5031 , G06F2217/84
摘要： A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.
摘要翻译： 集成电路（IC）配置的方法包括至少部分地基于给定IC设计的统计定时来确定一个或多个处置标准的步骤; 以及至少部分地基于至少一个测试结构的一个或多个测量来确定根据给定IC设计的给定IC是否满足所述一个或多个处置标准。
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公开(公告)号：US20120124535A1
公开(公告)日：2012-05-17
申请号：US12946950
申请日：2010-11-16
申请人： Jinjun Xiong , Vladimir Zolotov
发明人： Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G01R31/31718
摘要： At least one target metric is identified for an integrated circuit chip design for which manufacturing chip testing is to be optimized. At least one surrogate metric is also identified for the integrated circuit chip design for which manufacturing chip testing is to be optimized. A relationship between the at least one target metric and the at least one surrogate metric is modeled using a general joint probability density function. A chip disposition criterion is determined based on the general joint probability density function. The chip disposition criterion determines, for a given physical chip putatively manufactured in accordance with the design, based on the at least one surrogate metric for the given physical chip, whether the given physical chip is to be accepted or discarded during the manufacturing chip testing.
摘要翻译： 针对要优化制造芯片测试的集成电路芯片设计识别至少一个目标度量。 还针对要优化制造芯片测试的集成电路芯片设计识别至少一个替代度量。 使用一般联合概率密度函数来建模所述至少一个目标度量和所述至少一个代理度量之间的关系。 基于通用联合概率密度函数确定芯片配置准则。 芯片配置标准对于根据设计推定制造的给定物理芯片，基于给定物理芯片的至少一个替代度量来确定在制造芯片测试期间是否接受或丢弃给定的物理芯片。
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36.发明授权Integrated circuit product yield optimization using the results of performance path testing 有权集成电路产品产量优化使用性能路径测试的结果公开(公告)号：US09058034B2
公开(公告)日：2015-06-16
申请号：US13570285
申请日：2012-08-09
IPC分类号： G06F17/50 , G05B19/418
CPC分类号： G05B19/41875 , G05B2219/32182 , G05B2219/32187 , G05B2219/32208 , G05B2219/37224 , Y02P80/30 , Y02P90/22
摘要： Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.
摘要翻译： 公开了用于通过使生产线重新对中来优化集成电路产品产量的方法，系统和计算机程序产品的实施例，并且可选地，基于后期制造的结果调整晶片级芯片布置规则（例如，晶片级 或模块级）性能路径测试。 在实施例中，在后续制造性能路径测试期间获得的在线参数测量和性能测量之间进行相关。 然后，基于这种相关性，生产线可以重新居中。 可选地，在晶片级性能测试期间获得的性能测量和特别在模块级性能路径测试期间获得的性能测量之间进行附加的相关性，并且基于该附加相关性，可以对晶片级芯片布置规则进行调整 进一步降低产量损失。
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公开(公告)号：US08560980B2
公开(公告)日：2013-10-15
申请号：US12946950
申请日：2010-11-16
申请人： Jinjun Xiong , Vladimir Zolotov
发明人： Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G01R31/31718
摘要： At least one target metric is identified for an integrated circuit chip design for which manufacturing chip testing is to be optimized. At least one surrogate metric is also identified for the integrated circuit chip design for which manufacturing chip testing is to be optimized. A relationship between the at least one target metric and the at least one surrogate metric is modeled using a general joint probability density function. A chip disposition criterion is determined based on the general joint probability density function. The chip disposition criterion determines, for a given physical chip putatively manufactured in accordance with the design, based on the at least one surrogate metric for the given physical chip, whether the given physical chip is to be accepted or discarded during the manufacturing chip testing.
摘要翻译： 针对要优化制造芯片测试的集成电路芯片设计识别至少一个目标度量。 还针对要优化制造芯片测试的集成电路芯片设计识别至少一个替代度量。 使用一般联合概率密度函数来建模所述至少一个目标度量和所述至少一个代理度量之间的关系。 基于通用联合概率密度函数确定芯片配置准则。 芯片配置标准对于根据设计推定制造的给定物理芯片，基于给定物理芯片的至少一个代理度量来确定在制造芯片测试期间是否接受或丢弃给定的物理芯片。
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公开(公告)号：US08538715B2
公开(公告)日：2013-09-17
申请号：US12832206
申请日：2010-07-08
IPC分类号： G01R31/3181 , G06F11/30
CPC分类号： G01R31/31718 , G01R31/31725 , G06F17/5031 , G06F2217/84
摘要： A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.
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公开(公告)号：US20120010837A1
公开(公告)日：2012-01-12
申请号：US12832206
申请日：2010-07-08
CPC分类号： G01R31/31718 , G01R31/31725 , G06F17/5031 , G06F2217/84
摘要： A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.
摘要翻译： 集成电路（IC）配置的方法包括至少部分地基于给定IC设计的统计定时来确定一个或多个处置标准的步骤; 以及至少部分地基于至少一个测试结构的一个或多个测量来确定根据给定IC设计的给定IC是否满足所述一个或多个处置标准。
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公开(公告)号：US08964995B2
公开(公告)日：2015-02-24
申请号：US13607033
申请日：2012-09-07
CPC分类号： H04R29/00 , G07C5/008 , G07C5/0808
摘要： An acoustic monitoring system includes a portable acoustic detection device, a sound analysis device and a confidence level device. The portable acoustic detection device is capable of receiving sound at one or more locations near a sound-producing device. The sound analysis device receives the sound from the portable sound detection device, determines a diagnosis based on a comparison between the sound and pre-recorded sound data, and outputs the diagnosis to the portable acoustic detection device. The sound analysis device also determines a corrective action for inhibiting the sound, which is also output to the portable sound detection device. The confidence level device determines a confidence level of the diagnosis indicating a likelihood that the diagnosis is successfully diagnosed.
摘要翻译： 声学监测系统包括便携式声学检测装置，声音分析装置和置信水平装置。 便携式声学检测装置能够在声音产生装置附近的一个或多个位置处接收声音。 声音分析装置从便携式声音检测装置接收声音，根据声音和预先记录的声音数据之间的比较确定诊断，并将该诊断输出到便携式声音检测装置。 声音分析装置还确定还输出到便携式声音检测装置的用于抑制声音的校正动作。 置信水平装置确定诊断的置信水平，指示诊断成功诊断的可能性。
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