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    SEMICONDUCTOR DEVICE WITH ESD PROTECTION
    31.
    发明申请
    SEMICONDUCTOR DEVICE WITH ESD PROTECTION 有权
    具有ESD保护功能的半导体器件

    公开(公告)号：US20070253128A1

    公开(公告)日：2007-11-01

    申请号：US11741469

    申请日：2007-04-27

    Applicant: Marc Tiebout ,  Koen Mertens

    Inventor： Marc Tiebout ,  Koen Mertens

    IPC: H02H9/00

    CPC classification number: H03F1/523 ,  H03F1/223 ,  H03F3/3081

    Abstract: Semiconductor device having an amplifier. In one embodiment, the amplifier includes a first amplifier path including a first input and a second amplifier path including a second input. An inductance having a connectable node is connected between the first and second inputs, the connectable node being symmetrically connected between the first and second inputs. At least one ESD protection structure is connected to the connectable node. In one embodiment, the semiconductor device is used in a communications device.

    Abstract translation: 具有放大器的半导体器件。 在一个实施例中，放大器包括第一放大器路径，其包括第一输入和包括第二输入的第二放大器路径。 具有可连接节点的电感连接在第一和第二输入之间，可连接节点对称地连接在第一和第二输入之间。 至少一个ESD保护结构连接到可连接节点。 在一个实施例中，半导体器件用于通信设备中。

    Multifunction-RF-circuit
    32.
    发明申请
    Multifunction-RF-circuit 有权
    多功能RF电路

    公开(公告)号：US20070252753A1

    公开(公告)日：2007-11-01

    申请号：US11415397

    申请日：2006-04-28

    Applicant: Marc Tiebout

    Inventor： Marc Tiebout

    IPC: G01S13/00

    CPC classification number: G01S7/352 ,  H03F1/52 ,  H03F3/195 ,  H03F3/4521 ,  H03F2200/171 ,  H03F2203/45201 ,  H03F2203/45236

    Abstract: A multifunction RF circuit on a single semiconductor chip. The multifunction RF circuit includes a power amplifier circuit, a mixer circuit forming an integral part of the power amplifier circuit and a low-pass filter circuit. The power amplifier circuit may include two amplifier circuits.

    Abstract translation: 单个半导体芯片上的多功能RF电路。 多功能RF电路包括功率放大器电路，形成功率放大器电路的组成部分的混合电路和低通滤波器电路。 功率放大器电路可以包括两个放大器电路。

    Integrated circuit arrangement
    33.
    发明申请
    Integrated circuit arrangement 有权
    集成电路布置

    公开(公告)号：US20060103995A1

    公开(公告)日：2006-05-18

    申请号：US11264294

    申请日：2005-10-31

    Applicant: Thomas Benetik ,  Uwe Hodel ,  Christoph Kienmayer ,  Martin Streibl ,  Marc Tiebout

    Inventor： Thomas Benetik ,  Uwe Hodel ,  Christoph Kienmayer ,  Martin Streibl ,  Marc Tiebout

    IPC: H02H9/00

    CPC classification number: H01L27/0251

    Abstract: Integrated circuit arrangement having first and second signal input pads, to which a differential input signal is applied, and first and second signal outputs, at which a differential output signal is provided. The first signal output is coupled to the first signal input pad and the second signal output is coupled to the second signal input pad. A first capacitance is between the first and second signal input pads. First and second inductances are connected in series, are between the first and second signal input pads, and are connected in parallel with the first capacitance. A first terminal is at a first supply potential and a second terminal is at a second supply potential. A first electrostatic discharge element is between the first and second terminals. A second electrostatic discharge element is between the first terminal, on the one hand, and the first and second inductances, on the other hand.

    Abstract translation: 具有施加差分输入信号的第一和第二信号输入焊盘以及提供差分输出信号的第一和第二信号输出的集成电路装置。 第一信号输出耦合到第一信号输入焊盘，第二信号输出耦合到第二信号输入焊盘。 第一电容位于第一和第二信号输入焊盘之间。 第一和第二电感串联连接，位于第一和第二信号输入焊盘之间，并且与第一电容并联连接。 第一端子处于第一电源电位，第二端子处于第二电源电位。 第一静电放电元件在第一和第二端子之间。 另一方面，第二静电放电元件一方面在第一端子与第一和第二电感之间。

    Integrated circuit arrangement and circuit array
    34.
    发明授权
    Integrated circuit arrangement and circuit array 有权
    集成电路布置和电路阵列

    公开(公告)号：US08098471B2

    公开(公告)日：2012-01-17

    申请号：US11574066

    申请日：2005-08-09

    Applicant: Christoph Kienmayer ,  Martin Streibl ,  Marc Tiebout

    Inventor： Christoph Kienmayer ,  Martin Streibl ,  Marc Tiebout

    IPC: H02H3/22

    CPC classification number: H01L27/0251

    Abstract: One aspect is an integrated circuit arrangement. The arrangement includes a first terminal, which can be brought to a first supply potential, a second terminal, which can be brought to a second supply potential, and a supply potential path formed between the first terminal and the second terminal. There is an electrostatic discharge element at least in the supply potential path. There is a signal input pad, to which an input signal can be applied and a signal output, at an output signal can be provided. A first inductance is arranged between the signal input pad and the signal output, and a second inductance is arranged between the signal output and the first terminal.

    Abstract translation: 一个方面是集成电路装置。 该布置包括可以被带到第一电源电位的第一端子，可以被带到第二电源电位的第二端子和形成在第一端子和第二端子之间的电源路径。 至少在电源电位路径中存在静电放电元件。 有一个信号输入焊盘，可以在输出信号上提供输入信号并输出​​信号。 在信号输入焊盘和信号输出之间布置第一电感，并且在信号输出和第一端子之间布置第二电感。

    MOS transistor and semiconductor device
    35.
    发明授权
    MOS transistor and semiconductor device 有权
    MOS晶体管和半导体器件

    公开(公告)号：US07977709B2

    公开(公告)日：2011-07-12

    申请号：US11968552

    申请日：2008-01-02

    Applicant: Marc Tiebout ,  Daniel Kehrer ,  Domagoj Siprak ,  Pierre Mayr ,  Johannes Kunze ,  Christopher Weyers

    Inventor： Marc Tiebout ,  Daniel Kehrer ,  Domagoj Siprak ,  Pierre Mayr ,  Johannes Kunze ,  Christopher Weyers

    IPC: H01L27/18

    CPC classification number: H01L23/5283 ,  H01L23/4824 ,  H01L23/528 ,  H01L29/41725 ,  H01L2924/0002 ,  H01L2924/30105 ,  H01L2924/00

    Abstract: According to one embodiment of the present invention, a MOS transistor includes a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate structure is arranged above the channel regions. A source wiring structure is arranged above the source region and is connected to the source region. A drain wiring structure is arranged above the drain region and is connected to the drain region. The width of the source wiring structure is larger than the width of the drain wiring structure, and the height of the source wiring structure is smaller than the height of the drain wiring structure, or vice versa.

    Abstract translation: 根据本发明的一个实施例，MOS晶体管包括半导体层，其包括源极区，漏极区和设置在源极区和漏极区之间的沟道区。 栅极结构布置在沟道区域的上方。 源极布线结构布置在源极区域的上方并与源极区域连接。 漏极布线结构布置在漏极区上方并连接到漏极区。 源极布线结构的宽度大于漏极布线结构的宽度，源极布线结构的高度小于漏极布线结构的高度，反之亦然。

    Mixer circuit and method
    39.
    发明授权
    Mixer circuit and method 有权
    混频器电路及方法

    公开(公告)号：US07606538B2

    公开(公告)日：2009-10-20

    申请号：US11487205

    申请日：2006-07-14

    Applicant: Stefano Marsili ,  Marc Tiebout

    Inventor： Stefano Marsili ,  Marc Tiebout

    IPC: H04B1/04 ,  H04B17/00 ,  H03C1/62

    CPC classification number: H04B1/0475 ,  H04B2001/0491

    Abstract: A mixer circuit includes a mixer having input terminals and an output terminal, to provide an output signal by mixing input signals, wherein the mixer exhibits leakage. The circuit also includes a signal generator coupled to one of the input terminals of the mixer to provide a correction signal, an up-conversion mixer coupled to the mixer to provide an up-converted signal by mixing a test signal with the output signal of the mixer, and a down-conversion mixer coupled to the up-conversion mixer to provide a down-converted signal by down-converting the up-converted signal. A signal detector is coupled to the down-conversion mixer and detects a spurious signal in the down-converted signal, the spurious signal indicating the leakage, and a control unit is coupled to the signal detector and the signal generator to control generation of the correction signal depending on the detected spurious signal to compensate the leakage.

    Abstract translation: 混频器电路包括具有输入端和输出端的混频器，通过混合输入信号提供输出信号，其中混频器显示泄漏。 电路还包括耦合到混频器的一个输入端以提供校正信号的信号发生器，耦合到混频器的上转换混频器，通过将测试信号与 混频器和耦合到上变频混频器的下变频混频器，通过下变频上变频信号来提供下变频信号。 信号检测器耦合到下变频混频器并检测下变频信号中的寄生信号，指示泄漏的寄生信号，以及控制单元耦合到信号检测器和信号发生器以控制校正的产生 信号取决于检测到的杂散信号以补偿泄漏。

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