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    Semiconductor integrated circuit device
    1.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US08040187B2

    公开(公告)日：2011-10-18

    申请号：US12556115

    申请日：2009-09-09

    Applicant: Jun Deguchi ,  Naoki Kobayashi

    Inventor： Jun Deguchi ,  Naoki Kobayashi

    IPC: H03F3/04

    CPC classification number: H03F3/3028 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/505 ,  H03F2200/453 ,  H03F2203/45236 ,  H03F2203/45244 ,  H03F2203/45394 ,  H03F2203/45508 ,  H03F2203/45528 ,  H03F2203/45544 ,  H03F2203/45696 ,  H03F2203/45698 ,  H03F2203/45702

    Abstract: A semiconductor integrated circuit device constituting an inverting amplifier employs a cascode current source as a current source. In the semiconductor integrated circuit device, a high-potential-side transistor of the cascode current source and a low-potential-side transistor constituting an amplification portion are shared. The configuration can not only make an output impedance of the cascode current source high and improve current source characteristics but also make a minimum potential at a minimum potential point of the amplification portion low and ensure a sufficient power supply voltage margin.

    Abstract translation: 构成反相放大器的半导体集成电路器件采用共源共栅电流源作为电流源。 在半导体集成电路器件中，共享共源共栅电流源的高电位侧晶体管和构成放大部分的低电位侧晶体管。 该配置不仅可以使共源共栅电流源的输出阻抗高，并且提高电流源特性，而且使放大部分的最小电位处的最小电位降低，并确保足够的电源电压裕度。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    3.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20100244964A1

    公开(公告)日：2010-09-30

    申请号：US12556115

    申请日：2009-09-09

    Applicant: Jun Deguchi ,  Naoki Kobayashi

    Inventor： Jun Deguchi ,  Naoki Kobayashi

    IPC: H03F3/16

    CPC classification number: H03F3/3028 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/505 ,  H03F2200/453 ,  H03F2203/45236 ,  H03F2203/45244 ,  H03F2203/45394 ,  H03F2203/45508 ,  H03F2203/45528 ,  H03F2203/45544 ,  H03F2203/45696 ,  H03F2203/45698 ,  H03F2203/45702

    Abstract: A semiconductor integrated circuit device constituting an inverting amplifier employs a cascode current source as a current source. In the semiconductor integrated circuit device, a high-potential-side transistor of the cascode current source and a low-potential-side transistor constituting an amplification portion are shared. The configuration can not only make an output impedance of the cascode current source high and improve current source characteristics but also make a minimum potential at a minimum potential point of the amplification portion low and ensure a sufficient power supply voltage margin.

    Abstract translation: 构成反相放大器的半导体集成电路器件采用共源共栅电流源作为电流源。 在半导体集成电路器件中，共享共源共栅电流源的高电位侧晶体管和构成放大部分的低电位侧晶体管。 该配置不仅可以使共源共栅电流源的输出阻抗高，并且提高电流源特性，而且使放大部分的最小电位处的最小电位降低，并确保足够的电源电压裕度。

    Differential amplifier and display device using the same
    4.
    发明授权
    Differential amplifier and display device using the same 有权
    差分放大器和显示设备使用相同

    公开(公告)号：US07683714B2

    公开(公告)日：2010-03-23

    申请号：US11645612

    申请日：2006-12-27

    Applicant: Kouichi Nishimura ,  Atsushi Shimatani ,  Toshikazu Murata

    Inventor： Kouichi Nishimura ,  Atsushi Shimatani ,  Toshikazu Murata

    IPC: H03F3/45

    CPC classification number: H03F3/45192 ,  H03F3/3022 ,  H03F3/45744 ,  H03F2203/45236 ,  H03F2203/45281 ,  H03F2203/45342 ,  H03F2203/45354 ,  H03F2203/45684

    Abstract: Disclosed is a differential amplifier which comprises a differential pair comprising depletion-type first and second N-channel MOS transistors, a first current source that supplies a current for the differential pair, a current mirror circuit formed by transistor pairs connected in cascode fashion in two stages, for connecting an output pair of the differential pair in folded connection, second and third current sources connected to an input terminal of the current mirror circuit and an output terminal of the current circuit, respectively, and a buffer amplifier with that has an input terminal connected to the output terminal of the current mirror circuit and has an output terminal connected to an output terminal of the differential amplifier.

    Abstract translation: 公开了一种差分放大器，其包括包括耗尽型第一和第二N沟道MOS晶体管的差分对，提供用于差分对的电流的第一电流源，由以二阶共享方式连接的晶体管对形成的电流镜电路 用于连接折叠连接中的差分对的输出对，分别连接到电流镜电路的输入端的第二和第三电流源以及电流电路的输出端，以及具有输入的缓冲放大器 端子连接到电流镜电路的输出端，并具有连接到差分放大器的输出端的输出端。

    Programmable logic enabled dynamic offset cancellation
    6.
    发明授权
    Programmable logic enabled dynamic offset cancellation 有权
    可编程逻辑使能动态偏移消除

    公开(公告)号：US07321259B1

    公开(公告)日：2008-01-22

    申请号：US11245581

    申请日：2005-10-06

    Applicant: Sergey Yuryevich Shumarayev

    Inventor： Sergey Yuryevich Shumarayev

    IPC: H03F1/02 ,  H04B1/04

    CPC classification number: H03F3/45475 ,  H03F3/45183 ,  H03F3/45197 ,  H03F3/4521 ,  H03F3/45748 ,  H03F3/45973 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45236 ,  H03F2203/45366 ,  H03F2203/45482 ,  H03F2203/45494 ,  H03F2203/45681 ,  H03F2203/45702

    Abstract: Techniques and circuitry are provided for programmatically controlling signal offsets in integrated circuitry. In one embodiment, a buffer circuit having an offset cancellation circuit receives a signal and transmits the signal to programmable logic circuit. The programmable logic uses programmable resources and/or one or more algorithms to measure integrated circuit operations and/or operational errors associated with the offset. The control signal is fed back to an input of the offset cancellation circuit. In one embodiment, the offset cancellation circuit adjusts the offset of the signal in response to the magnitude of the offset cancellation signal received until changes associated with the offset and/or the magnitude of the operational errors are no longer attributable to the offset.

    Abstract translation: 提供技术和电路用于以编程方式控制集成电路中的信号偏移。 在一个实施例中，具有偏移消除电路的缓冲器电路接收信号并将该信号发送到可编程逻辑电路。 可编程逻辑使用可编程资源和/或一个或多个算法来测量与偏移相关联的集成电路操作和/或操作错误。 控制信号被反馈到偏移消除电路的输入端。 在一个实施例中，偏移消除电路响应于所接收的偏移消除信号的大小来调整信号的偏移，直到与偏移相关联的变化和/或操作误差的大小不再归因于偏移。

    Circuits and techniques for conditioning differential signals
    7.
    发明授权
    Circuits and techniques for conditioning differential signals 失效
    差分信号调理电路和技术

    公开(公告)号：US06985021B1

    公开(公告)日：2006-01-10

    申请号：US10652521

    申请日：2003-08-29

    Applicant: Arch Zaliznyak ,  William Bereza ,  Henry Lui ,  Chong Lee ,  Rakesh Patel

    Inventor： Arch Zaliznyak ,  William Bereza ,  Henry Lui ,  Chong Lee ,  Rakesh Patel

    IPC: H03F3/45

    CPC classification number: H03F3/45475 ,  H03F3/4521 ,  H03F3/45928 ,  H03F2200/513 ,  H03F2203/45088 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45236 ,  H03F2203/45366 ,  H03F2203/45544 ,  H03F2203/45561 ,  H03F2203/45586 ,  H03F2203/45592 ,  H03F2203/45594 ,  H03F2203/45616 ,  H03K19/003

    Abstract: Circuitry is provided that conditions a differential input signal such that when the signal is received by a multi-standard differential input buffer, the buffer is able to process the conditioned signal without pronounced increases in propagation delay, thereby keeping signal jitter to a minimum. The circuitry further enables input buffers to operate according to desired operating parameters even when the supply voltage powering the input buffer is relatively low. The circuitry operates by shifting the common-mode voltage to a range that puts the input buffer in a favorable common-mode voltage range of operation. The circuitry may be coupled with a programmably controlled amplifier that amplifies the amplitude of the conditioned differential signal prior to being received by the input buffer. Amplifying the signal prevents problems typically associated with data-dependent jitter and intersymbol interference by boosting the voltage amplitude to a level that is readily processed by the input buffer.

    Abstract translation: 提供电路，其规定差分输入信号，使得当信号被多标准差分输入缓冲器接收时，缓冲器能够处理调节后的信号而传播延迟不会明显增加，从而将信号抖动保持在最小。 该电路还使输入缓冲器能够根据期望的操作参数进行操作，即使为输入缓冲器供电的电源电压相对较低。 电路通过将共模电压移动到使输入缓冲器处于有利的共模电压操作范围的范围来工作。 电路可以与可编程控制的放大器耦合，放大器在由输入缓冲器接收之前放大经调节的差分信号的幅度。 通过将电压幅度升高到输入缓冲器容易处理的电平，放大信号可防止通常与数据相关的抖动和符号间干扰相关的问题。

    ENHANCED TRANSCONDUCTANCE CIRCUIT
    9.
    发明申请
    ENHANCED TRANSCONDUCTANCE CIRCUIT 审中-公开
    增强型交叉电路

    公开(公告)号：US20140159813A1

    公开(公告)日：2014-06-12

    申请号：US14182799

    申请日：2014-02-18

    Applicant: Sandro HERRERA

    Inventor： Sandro HERRERA

    IPC: H03F3/45

    CPC classification number: H03F3/45071 ,  H03F1/3211 ,  H03F3/4508 ,  H03F3/45085 ,  H03F2203/45236 ,  H03F2203/45352 ,  H03F2203/45366

    Abstract: A transconductance circuit that improves linearity and output current over a wider range of input voltages than prior designs. The transconductance circuit may include first and second sets of paired differential transistors. In each set, emitters of the paired transistors may be commonly coupled to corresponding nodes of a common impedance, and collectors may be coupled to output terminals of the transconductance circuit. The circuit may further include first and second sets of doublet differential transistor pairs, each doublet pair having transistors of different sizes. Each doublet pair may have current sources coupled between commonly coupled emitters and a source potential. Respective collectors for each doublet pair may be coupled to the output terminals of the transconductance circuit. A pair of voltage followers may be provided to replicate corresponding input voltages across corresponding bases of the differential transistor pairs and the doublet transistor pairs.

    Abstract translation: 一种跨导电路，可在比现有设计更宽的输入电压范围内提高线性度和输出电流。 跨导电路可以包括第一组和第二组成对的差分晶体管。 在每组中，成对晶体管的发射极可以共同耦合到公共阻抗的对应节点，并且集电极可以耦合到跨导电路的输出端子。 电路还可以包括第一组和第二组双差分晶体管对，每个双对具有不同尺寸的晶体管。 每个双引线对可以具有耦合在共同耦合的发射极和源电位之间的电流源。 每个双绞线对的各个集电极可以耦合到跨导电路的输出端子。 可以提供一对电压跟随器来复制跨越差分晶体管对和双晶体管对的相应基极的对应输入电压。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    10.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20120112840A1

    公开(公告)日：2012-05-10

    申请号：US13354757

    申请日：2012-01-20

    Applicant: Jun DEGUCHI ,  Naoki Kobayashi

    Inventor： Jun DEGUCHI ,  Naoki Kobayashi

    IPC: H03F3/04 ,  H03F1/22

    CPC classification number: H03F3/3028 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/505 ,  H03F2200/453 ,  H03F2203/45236 ,  H03F2203/45244 ,  H03F2203/45394 ,  H03F2203/45508 ,  H03F2203/45528 ,  H03F2203/45544 ,  H03F2203/45696 ,  H03F2203/45698 ,  H03F2203/45702

    Abstract: A semiconductor integrated circuit device constituting an inverting amplifier employs a cascode current source as a current source. In the semiconductor integrated circuit device, a high-potential-side transistor of the cascode current source and a low-potential-side transistor constituting an amplification portion are shared. The configuration can not only make an output impedance of the cascode current source high and improve current source characteristics but also make a minimum potential at a minimum potential point of the amplification portion low and ensure a sufficient power supply voltage margin.

    Abstract translation: 构成反相放大器的半导体集成电路器件采用共源共栅电流源作为电流源。 在半导体集成电路器件中，共享共源共栅电流源的高电位侧晶体管和构成放大部分的低电位侧晶体管。 该配置不仅可以使共源共栅电流源的输出阻抗高，并且提高电流源特性，而且使放大部分的最小电位处的最小电位降低，并确保足够的电源电压裕度。

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