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    Fast Hopping Frequency Synthesizer
    4.
    发明申请
    Fast Hopping Frequency Synthesizer 有权
    快速跳频合成器

    公开(公告)号：US20090088113A1

    公开(公告)日：2009-04-02

    申请号：US11863037

    申请日：2007-09-27

    Applicant: Stefano Marsili ,  Marc Tiebout ,  Andrea Bevilacqua ,  Sterano Dal Toso

    Inventor： Stefano Marsili ,  Marc Tiebout ,  Andrea Bevilacqua ,  Sterano Dal Toso

    IPC: H04B1/06 ,  H03B27/00 ,  H03B5/08

    CPC classification number: H04B1/7136 ,  H03L7/06 ,  H04B2001/71362

    Abstract: Apparatus and systems for synthesizing frequencies for use in a fast hopping wireless communications system. A frequency synthesizer comprises a plurality of oscillators with each oscillator having a first input coupled to a reference clock frequency signal, and a signal selector having a control signal input and a plurality of reference clock inputs with each reference clock input coupled to an output from an oscillator. Each oscillator produces a reference frequency that is a harmonic of a reference clock frequency of the reference clock frequency signal, and the signal selector couples a reference clock input to an output based on a control signal provided by the control signal input.

    Abstract translation: 用于合成频率以用于快速跳频无线通信系统的装置和系统。 频率合成器包括多个振荡器，每个振荡器具有耦合到参考时钟频率信号的第一输入端，以及信号选择器，具有控制信号输入和多个参考时钟输入，每个参考时钟输入耦合到来自 振荡器 每个振荡器产生参考频率，其是参考时钟频率信号的参考时钟频率的谐波，并且信号选择器基于由控制信号输入提供的控制信号将参考时钟输入耦合到输出。

    Integrated, tunable capacitance device
    6.
    发明授权
    Integrated, tunable capacitance device 失效
    集成可调电容器件

    公开(公告)号：US07019384B2

    公开(公告)日：2006-03-28

    申请号：US10678385

    申请日：2003-10-03

    Applicant: Judith Maget ,  Marc Tiebout

    Inventor： Judith Maget ,  Marc Tiebout

    IPC: H01L29/93

    CPC classification number: H01L29/94 ,  H01L27/0808

    Abstract: An integrated, tunable capacitance device includes a semiconductor region, which is, preferably, N-doped, formed in a semiconductor body, having an insulating thick oxide region, which areally adjoins the main side of the semiconductor body, and having a thin oxide region, which, likewise, adjoins the main side and is disposed above the semiconductor region and also has a smaller layer thickness than the thick oxide region. A gate electrode is provided on the thin oxide region and terminal regions are provided in the semiconductor region. The capacitance described has a larger tuning range compared with transistor varactors. The integrated, tunable capacitance can be used, for example, in LC oscillators of integrated VCOs.

    Abstract translation: 集成的可调谐电容器件包括：半导体区域，优选地，N掺杂形成在半导体本体中，具有绝缘的厚氧化物区域，该半导体区域与半导体本体的主侧邻接并具有薄的氧化物区域 ，其同样邻接主侧并且设置在半导体区域的上方，并且还具有比厚氧化物区域更小的层厚度。 在薄氧化物区域上设置栅电极，在半导体区域设置端子区域。 与晶体管可变电抗器相比，所描述的电容具有较大的调谐范围。 集成的可调谐电容可用于例如集成VCO的LC振荡器。

    Voltage-controlled capacitor
    7.
    发明授权
    Voltage-controlled capacitor 有权
    压控电容

    公开(公告)号：US06646499B2

    公开(公告)日：2003-11-11

    申请号：US10288388

    申请日：2002-11-05

    Applicant: Marc Tiebout

    Inventor： Marc Tiebout

    IPC: H03K1700

    CPC classification number: H03H11/483

    Abstract: A voltage-controlled capacitor is configured in such a way that it contains two varactors connected in parallel. The varactors are connected in such a way that a capacitance is controlled by differential signals. This layout results in a voltage-controlled capacitor that has an optimally low sensitivity to interference.

    Abstract translation: 压控电容器被配置成使得它包含两个并联连接的变容二极管。 变容二极管的连接方式是电容由差分信号控制。 这种布局导致了对干扰敏感性最佳的压控电容器。

    Fast hopping frequency synthesizer
    8.
    发明授权
    Fast hopping frequency synthesizer 有权
    快跳频率合成器

    公开(公告)号：US07940830B2

    公开(公告)日：2011-05-10

    申请号：US11863037

    申请日：2007-09-27

    Applicant: Stefano Marsili ,  Marc Tiebout ,  Andrea Bevilacqua ,  Stefano Dal Toso

    Inventor： Stefano Marsili ,  Marc Tiebout ,  Andrea Bevilacqua ,  Stefano Dal Toso

    IPC: H04B1/00

    CPC classification number: H04B1/7136 ,  H03L7/06 ,  H04B2001/71362

    Abstract: Apparatus and systems for synthesizing frequencies for use in a fast hopping wireless communications system. A frequency synthesizer comprises a plurality of oscillators with each oscillator having a first input coupled to a reference clock frequency signal, and a signal selector having a control signal input and a plurality of reference clock inputs with each reference clock input coupled to an output from an oscillator. Each oscillator produces a reference frequency that is a harmonic of a reference clock frequency of the reference clock frequency signal, and the signal selector couples a reference clock input to an output based on a control signal provided by the control signal input.

    Abstract translation: 用于合成频率以用于快速跳跃无线通信系统的装置和系统。 频率合成器包括多个振荡器，每个振荡器具有耦合到参考时钟频率信号的第一输入端，以及信号选择器，具有控制信号输入和多个参考时钟输入，每个参考时钟输入耦合到来自 振荡器 每个振荡器产生参考频率，其是参考时钟频率信号的参考时钟频率的谐波，并且信号选择器基于由控制信号输入提供的控制信号将参考时钟输入耦合到输出。

    DeMOS DCO
    9.
    发明申请
    DeMOS DCO 审中-公开

    公开(公告)号：US20110043294A1

    公开(公告)日：2011-02-24

    申请号：US12543637

    申请日：2009-08-19

    Applicant: Gerhard KNOBLINGER ,  Marc TIEBOUT ,  Franz KUTTNER

    Inventor： Gerhard KNOBLINGER ,  Marc TIEBOUT ,  Franz KUTTNER

    IPC: H03B5/12

    CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1265

    Abstract: The present disclosure relates voltage controlled oscillators (VCO) and digitally controlled oscillators (DCO). In one implementation, a VCO is implemented with drain extended MOS transistors (DeMOS). In another implementation, a DCO is implemented with DeMOS devices.

    Abstract translation: 本公开涉及压控振荡器（VCO）和数字控制振荡器（DCO）。 在一个实现中，使用漏极扩展MOS晶体管（DeMOS）实现VCO。 在另一个实现中，使用DeMOS设备实现DCO。

    MOS Transistor and Semiconductor Device
    10.
    发明申请
    MOS Transistor and Semiconductor Device 有权
    MOS晶体管和半导体器件

    公开(公告)号：US20090166681A1

    公开(公告)日：2009-07-02

    申请号：US11968552

    申请日：2008-01-02

    Applicant: Marc Tiebout ,  Daniel Kehrer ,  Domagoj Siprak ,  Pierre Mayr ,  Johannes Kunze ,  Christopher Weyers

    Inventor： Marc Tiebout ,  Daniel Kehrer ,  Domagoj Siprak ,  Pierre Mayr ,  Johannes Kunze ,  Christopher Weyers

    IPC: H01L29/78

    CPC classification number: H01L23/5283 ,  H01L23/4824 ,  H01L23/528 ,  H01L29/41725 ,  H01L2924/0002 ,  H01L2924/30105 ,  H01L2924/00

    Abstract: According to one embodiment of the present invention, a MOS transistor includes a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate structure is arranged above the channel regions. A source wiring structure is arranged above the source region and is connected to the source region. A drain wiring structure is arranged above the drain region and is connected to the drain region. The width of the source wiring structure is larger than the width of the drain wiring structure, and the height of the source wiring structure is smaller than the height of the drain wiring structure, or vice versa.

    Abstract translation: 根据本发明的一个实施例，MOS晶体管包括半导体层，其包括源极区，漏极区和设置在源极区和漏极区之间的沟道区。 栅极结构布置在沟道区域的上方。 源极布线结构布置在源极区域的上方并与源极区域连接。 漏极布线结构布置在漏极区上方并连接到漏极区。 源极布线结构的宽度大于漏极布线结构的宽度，源极布线结构的高度小于漏极布线结构的高度，反之亦然。

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