公开(公告)号：US20240381537A1

公开(公告)日：2024-11-14

申请号：US18632413

申请日：2024-04-11

Applicant: KYOCERA AVX Components Corporation

Inventor： Cory Nelson ,  Jessica Parry

IPC: H05K1/18

Abstract: Single layer capacitors and circuit boards are provided. A circuit board can include a circuit board substrate having a mounting surface and a single layer capacitor at least partially embedded within the circuit board substrate. The single layer capacitor can include a first passivation layer formed over at least a portion of a first surface of a substrate, a first conductive layer formed over at least a portion of the first passivation layer, and a second conductive layer formed over at least a portion of a second surface of the substrate. A method for forming a single layer capacitor can include depositing a passivation layer over at least a portion of a substrate first surface, depositing a first conductive layer over at least a portion of the passivation layer, and depositing a second conductive layer over at least a portion of a substrate second surface, opposite the first surface.

公开(公告)号：US12080809B2

公开(公告)日：2024-09-03

申请号：US17722465

申请日：2022-04-18

Applicant: KYOCERA AVX Components Corporation

Inventor： Cory Nelson

IPC: H01L29/94 ,  H01L29/66

CPC classification number: H01L29/94 ,  H01L29/66181

Abstract: A metal-oxide-semiconductor (MOS) capacitor can include a substrate including a semiconductor material, an oxide layer formed on a surface of the substrate, a conductive layer formed over at least a portion of the oxide layer, a first terminal connected with the surface of the substrate, and a second terminal connected with the conductive layer. The oxide layer can be connected in series between the substrate and the conductive layer to form a capacitor between the first terminal and the second terminal. Each of the first terminal and the second terminal can be exposed along the surface of the substrate for surface mounting the capacitor. The MOS capacitor can exhibit excellent high frequency performance. For example, an insertion loss of the MOS capacitor can be greater than about −0.75 dB for frequencies ranging from about 5 GHz to about 40 GHz.

公开(公告)号：US20240249880A1

公开(公告)日：2024-07-25

申请号：US18408647

申请日：2024-01-10

Applicant: KYOCERA AVX Components Corporation

Inventor： Cory Nelson ,  Jeffrey Horn ,  Marianne Berolini

IPC: H01G4/012 ,  H01G4/30

CPC classification number: H01G4/012 ,  H01G4/30

Abstract: Multilayer capacitors are provided. For example, a multilayer capacitor may include first and second terminals adjacent first and second opposing end surfaces, respectively, and a plurality of active electrode layers, each active electrode layer including a first active electrode electrically connected with the first terminal and a second active electrode electrically connected with the second terminal. The first active electrode may be spaced apart from the second active electrode in a lengthwise direction to form an active electrode end gap. The multilayer capacitor also may include a plurality of floating electrode layers, including topmost and bottommost floating electrode layers. The plurality of active electrode layers may be an odd number such that a topmost active electrode layer is disposed between the topmost floating electrode layer and a top surface and a bottommost active electrode layer is disposed between the bottommost floating electrode layer and a bottom surface.

公开(公告)号：US20230326923A1

公开(公告)日：2023-10-12

申请号：US17969835

申请日：2022-10-20

Applicant: KYOCERA AVX Components Corporation

Inventor： Cory Nelson

IPC: H01L27/08

CPC classification number: H01L27/0811 ,  H01L28/60

Abstract: A combined metal-oxide-semiconductor (MOS) and metal-insulator-semiconductor (MIS) capacitor assembly is provided. The capacitor assembly includes a substrate comprising a semiconductor material; an oxide layer formed on a surface of the substrate; and an insulator layer formed over at least a portion of the oxide layer. The capacitor assembly further includes first and second conductive terminals, and a third terminal connected with the substrate. The oxide layer is connected in series between the substrate and the first conductive layer to form a first capacitor between the first terminal and the third terminal. The insulator layer is connected in series between the substrate and the second conductive layer to form a second capacitor between the second terminal and the third terminal.

公开(公告)号：US20230140344A1

公开(公告)日：2023-05-04

申请号：US17969821

申请日：2022-10-20

Applicant: KYOCERA AVX Components Corporation

Inventor： Cory Nelson

IPC: H01L29/94 ,  H01L29/66 ,  H01G4/012 ,  H01G4/10 ,  H01L29/417

Abstract: A capacitor assembly includes a primary capacitor and a secondary capacitor formed on a substrate. The primary capacitor and the secondary capacitor can be connected by a conduction line. The conduction line can be formed from a thin metal connection. The conduction line can be severed, i.e., trimmed, to finely tune a capacitance value of the capacitor assembly. The capacitor assembly can allow for tighter tolerance and wider variance of the capacitance value of the capacitor assembly. The capacitor assembly can be trimmed after installing the capacitor assembly in the circuit, thereby enabling fine tuning of the capacitance value of the capacitor assembly for applications requiring precision tunable capacitance.

公开(公告)号：US20220418081A1

公开(公告)日：2022-12-29

申请号：US17849841

申请日：2022-06-27

Applicant: KYOCERA AVX Components Corporation

Inventor： Cory Nelson ,  Jeff Borgman ,  Marianne Berolini

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/30 ,  H05K3/40 ,  H05K1/18

Abstract: A heat sink component can include a body including a thermally conductive material that is electrically non-conductive, a lower conductive layer formed over a bottom surface of the body and electrically connected with the ground plane layer, and an upper conductive layer formed over a top surface of the body. The heat sink component can have a length in an X-direction that is parallel with the top surface of the body and a thickness in a direction perpendicular to the top surface. A ratio of the length to the thickness can be greater than about 7.

公开(公告)号：US20220367733A1

公开(公告)日：2022-11-17

申请号：US17740417

申请日：2022-05-10

Applicant: KYOCERA AVX Components Corporation

Inventor： Cory Nelson ,  Jeff Borgman

IPC: H01L29/94 ,  H01L29/66

Abstract: A semiconductor-based capacitor can include a substrate including a semiconductor material, an oxide layer formed over the substrate, a conductive layer formed over at least a portion of the oxide layer, a plurality of distinct coplanar upper terminals, and a lower terminal. The upper terminals and the lower terminal can be exposed along the top and bottom surfaces of the substrate, respectively, for embedding the capacitor in a substrate such as a circuit board. The semiconductor-based capacitor can be sufficiently miniaturized to be embeddable within a circuit board while providing superior capacitance values without compromising the integrity of the capacitor. For example, each of the upper terminals can have a maximum width and a thickness normal to the maximum width, and a ratio of the width to the thickness can be greater than about 80:1 to prevent physical damage to the capacitor from warping or cracking.