公开(公告)号：US20120326798A1

公开(公告)日：2012-12-27

申请号：US13168512

申请日：2011-06-24

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: H01P3/08 ,  H05K13/00 ,  H05K9/00 ,  G06F17/50

CPC classification number: H01L23/5222 ,  H01L23/5225 ,  H01L23/66 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01P1/184 ,  Y10T29/49117 ,  H01L2924/00

Abstract: A transmission wiring structure, associated design structure and associated method for forming the same. A structure is disclosed having: a plurality of wiring levels formed on a semiconductor substrate; a pair of adjacent first and second signal lines located in the wiring levels, wherein the first signal line comprises a first portion formed on a first wiring level and a second portion formed on a second wiring level; a primary dielectric structure having a first dielectric constant located between the first portion and a ground shield; and a secondary dielectric structure having a second dielectric constant different than the first dielectric constant, the secondary dielectric structure located between the second portion and the ground shield, and the second dielectric layer extending co-planar with the second portion and having a length that is substantially the same as the second portion.

Abstract translation: 一种传输线路结构，相关设计结构及其相关方法。 公开了一种结构，其具有：形成在半导体衬底上的多个布线层; 位于布线层中的一对相邻的第一和第二信号线，其中第一信号线包括形成在第一布线层上的第一部分和形成在第二布线层上的第二部分; 第一介电结构，其具有位于第一部分和接地屏蔽之间的第一介电常数; 以及具有不同于所述第一介电常数的第二介电常数的次级介电结构，所述第二介电结构位于所述第二部分和所述接地屏蔽之间，并且所述第二电介质层与所述第二部分共面延伸并且具有长度为 基本上与第二部分相同。

公开(公告)号：US08232115B2

公开(公告)日：2012-07-31

申请号：US12566726

申请日：2009-09-25

Applicant: Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

Inventor： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L21/76898

Abstract: A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.

Abstract translation: 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。 确定半导体芯片中的硅通孔（TSV）的深度的方法包括将第一TSV蚀刻到半导体芯片中; 形成第一通道，所述第一通道包括所述第一TSV，电连接到所述第一TSV的第一触点和第二触点; 将电流源连接到第二触点; 确定跨越第一通道的电阻; 以及基于所述第一通道的电阻确定所述第一TSV的深度。

公开(公告)号：US08101494B2

公开(公告)日：2012-01-24

申请号：US12191379

申请日：2008-08-14

Applicant: David S. Collins ,  Kai D. Feng ,  Zhong-Xiang He ,  Peter J. Lindgren ,  Robert M. Rassel

Inventor： David S. Collins ,  Kai D. Feng ,  Zhong-Xiang He ,  Peter J. Lindgren ,  Robert M. Rassel

IPC: H01L21/20

CPC classification number: H01L29/945 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/642 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.

Abstract translation: 制造半导体结构的方法包括在衬底中形成至少具有不同深度的第一沟槽和第二沟槽，在第一沟槽中形成电容器，并在第二沟槽中形成通孔。 半导体结构包括布置在形成在衬底中的第一沟槽中的电容器和布置在形成于衬底中的第二沟槽中的通孔。 第一和第二沟槽在衬底中具有不同的深度。

公开(公告)号：US08012814B2

公开(公告)日：2011-09-06

申请号：US12188366

申请日：2008-08-08

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

IPC: H01L21/84

CPC classification number: H01L21/84 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/1203 ,  H01L27/1207

Abstract: A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.

Abstract translation: 保护绝缘体上半导体（SOI）衬底的顶部半导体层的第一部分，同时去除顶部半导体层的第二部分以暴露掩埋的绝缘体层。 形成包括位于顶部半导体层的第一部分上方的栅极电介质和栅电极的第一场效应晶体管。 暴露的掩埋绝缘体层的一部分用作第二场效应晶体管的栅极电介质。 在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。 在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。

公开(公告)号：US20100041203A1

公开(公告)日：2010-02-18

申请号：US12191379

申请日：2008-08-14

Applicant: David S. Collins ,  Kai D. Feng ,  Zhong-Xiang He ,  Peter J. Lindgren ,  Robert M. Rassel

Inventor： David S. Collins ,  Kai D. Feng ,  Zhong-Xiang He ,  Peter J. Lindgren ,  Robert M. Rassel

IPC: H01L21/20

CPC classification number: H01L29/945 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/642 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.

Abstract translation: 制造半导体结构的方法包括在衬底中形成至少具有不同深度的第一沟槽和第二沟槽，在第一沟槽中形成电容器，并在第二沟槽中形成通孔。 半导体结构包括布置在形成在衬底中的第一沟槽中的电容器和布置在形成于衬底中的第二沟槽中的通孔。 第一和第二沟槽在衬底中具有不同的深度。

公开(公告)号：US20100035370A1

公开(公告)日：2010-02-11

申请号：US12187436

申请日：2008-08-07

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

IPC: H01L21/00

CPC classification number: H01Q1/40 ,  H01Q9/28

Abstract: A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is formed on a front side of a semiconductor substrate. At least one through substrate via provides electrical connection between the transceiver and the backside of the semiconductor substrate. The antenna, which is connected to the transceiver, is formed in a dielectric layer on the front side. The reflector plate is connected to the through substrate via, and is formed on the backside. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate trenches may be formed and filled with a dielectric material to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency.

Abstract translation: 提供集成收发器，天线和接收器的半导体芯片。 收发器形成在半导体衬底的前侧。 至少一个通过衬底通孔提供收发器和半导体衬底的背面之间的电连接。 连接到收发器的天线形成在前侧的电介质层中。 反射板与穿通基板连接，并形成在背面。 反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。 通过衬底沟槽的阵列可以形成并填充介电材料，以减小天线和反射板之间的材料的有效介电常数，从而减小毫米波的波长并提高辐射效率。

公开(公告)号：US20100032761A1

公开(公告)日：2010-02-11

申请号：US12188381

申请日：2008-08-08

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

IPC: H01L27/12

CPC classification number: H01L27/088 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/1207

Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

Abstract translation: 第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。 第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。 在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。 在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。 第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。 还提供了用于半导体结构的设计结构。

公开(公告)号：US07571637B2

公开(公告)日：2009-08-11

申请号：US11926241

申请日：2007-10-29

Applicant: Fen Chen ,  Kai D. Feng

Inventor： Fen Chen ,  Kai D. Feng

IPC: G01N5/02

CPC classification number: G01N27/223

Abstract: A design structure for an on-chip real-time moisture detection circuitry for monitoring ingress of moisture into an integrated circuit chip during the operational lifetime of the chip. The moisture detection circuitry includes one or more moisture-sensing units and a common moisture monitor for monitoring the state of each moisture-sensing units. The moisture monitor can be configured to provided a real-time moisture-detected signal for signaling that moisture ingress into the integrated circuit chip has occurred.

Abstract translation: 一种片上实时水分检测电路的设计结构，用于在芯片的使用寿命期间监测水分进入集成电路芯片的情况。 湿度检测电路包括一个或多个湿度感测单元和用于监测每个湿度感测单元的状态的公共湿度监视器。 水分监测器可以被配置为提供实时湿度检测信号，用于发信号通知已经发生湿气进入集成电路芯片。

公开(公告)号：US20090113361A1

公开(公告)日：2009-04-30

申请号：US11928093

申请日：2007-10-30

Applicant: Kai D. Feng ,  Anjali R. Malladi

Inventor： Kai D. Feng ,  Anjali R. Malladi

IPC: G06F17/50 ,  H03L7/099

CPC classification number: H03L7/099 ,  H03L7/10 ,  H03L2207/06

Abstract: A design structure for an integrated circuit including a phase-locked loop (PLL) circuit responsive to a voltage controlled oscillator (VCO) frequency band selection circuit that provides automatic frequency band selection in real time to account for run-time variations, such as power supply and temperature variations over time. The PLL includes a charge pump and an LC tank circuit that provides the automatic frequency band selection based on a VCO control voltage signal supplied by the charge pump.

Abstract translation: 一种用于集成电路的设计结构，包括响应于压控振荡器（VCO）频带选择电路的锁相环（PLL）电路，其实时提供自动频带选择以解决运行时间变化，例如功率 供应和温度随时间变化。 PLL包括电荷泵和LC槽电路，其基于由电荷泵提供的VCO控制电压信号提供自动频带选择。

公开(公告)号：US20080233681A1

公开(公告)日：2008-09-25

申请号：US12133442

申请日：2008-06-05

Applicant: Elie Awad ,  Mariette A. Awad ,  Kai D. Feng

Inventor： Elie Awad ,  Mariette A. Awad ,  Kai D. Feng

IPC: H01L21/00

CPC classification number: H01L24/02 ,  H01L23/562 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025

Abstract: A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within the substrate, the first structure having an upper surface; and a stress diverting structure proximate the first structure and within the first layer, the stress diverting structure providing a low mechanical stress region at the upper surface of the first structure when a physical load is applied to the first structure, wherein said low mechanical stress region comprises stress values below the stress values in areas not protected by the stress diverting structure. The stress diverting structure comprises a second material having a second modulus of elasticity less than the first modulus of elasticity, the second material selectively formed over the upper surface of the first structure for diverting mechanical stress created by the physical load applied to the first structure.

Abstract translation: 一种半导体结构，包括：基板，包括第一层，所述第一层包括具有第一弹性模量的第一材料; 包括导体并形成在所述基板内的第一结构，所述第一结构具有上表面; 以及靠近所述第一结构并且在所述第一层内的应力转向结构，所述应力转向结构在向所述第一结构施加物理载荷时在所述第一结构的上表面处提供低机械应力区域，其中所述低机械应力区域 包括低于应力转移结构保护区域的应力值。 应力转向结构包括具有小于第一弹性模量的第二弹性模量的第二材料，第二材料选择性地形成在第一结构的上表面上，用于转移由施加到第一结构的物理负载产生的机械应力。