公开(公告)号：US20100062582A1

公开(公告)日：2010-03-11

申请号：US12516684

申请日：2007-08-13

申请人： Kazuhiro Fujikawa

发明人： Kazuhiro Fujikawa

IPC分类号： H01L21/04

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66068

摘要： There is provided a method of manufacturing a silicon carbide semiconductor device including the steps of: in a semiconductor stacked substrate including a first conductivity type silicon carbide crystal substrate, a first conductivity type silicon carbide crystal layer, a second conductivity type silicon carbide crystal layer, and a first conductivity type semiconductor region, forming a trench extending through the first conductivity type semiconductor region and the second conductivity type silicon carbide crystal layer into the first conductivity type silicon carbide crystal layer defined as a bottom surface; forming a silicon film on at least a part of the trench; heating the semiconductor stacked substrate having the silicon film formed to a temperature that is not less than the melting temperature of the silicon film; removing the heated silicon film; forming a gate insulating film on a surface exposed after the silicon film is removed; and forming a gate electrode layer on a surface of the gate insulating film.

摘要翻译： 提供一种制造碳化硅半导体器件的方法，包括以下步骤：在包括第一导电型碳化硅晶体衬底，第一导电型碳化硅晶体层，第二导电型碳化硅晶体层的半导体堆叠衬底中， 以及第一导电型半导体区域，在形成为底面的第一导电型碳化硅晶层中形成延伸穿过第一导电型半导体区域和第二导电型碳化硅晶体层的沟槽; 在所述沟槽的至少一部分上形成硅膜; 将形成有硅膜的半导体层叠基板加热到不低于硅膜的熔融温度的温度; 去除加热的硅膜; 在除去硅膜后露出的表面上形成栅极绝缘膜; 以及在栅极绝缘膜的表面上形成栅电极层。

公开(公告)号：US20100035411A1

公开(公告)日：2010-02-11

申请号：US12444551

申请日：2007-08-13

申请人： Kazuhiro Fujikawa ,  Takeyoshi Masuda

发明人： Kazuhiro Fujikawa ,  Takeyoshi Masuda

IPC分类号： H01L21/04

CPC分类号： H01L29/808 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66901 ,  Y10S438/931

摘要： A method of manufacturing an SiC semiconductor device includes the steps of ion implanting a dopant at least in a part of a surface of an SiC single crystal, forming an Si film on the surface of the ion-implanted SiC single crystal, and heating the SiC single crystal on which the Si film is formed to a temperature not less than a melting temperature of the Si film.

摘要翻译： 一种制造SiC半导体器件的方法包括以下步骤：在SiC单晶的至少一部分表面上离子注入掺杂剂，在离子注入的SiC单晶的表面上形成Si膜，并加热SiC 在其上形成Si膜的单晶，其温度不低于Si膜的熔融温度。

公开(公告)号：US20090154210A1

公开(公告)日：2009-06-18

申请号：US11719678

申请日：2005-09-30

申请人： Kazuhiro Fujikawa

发明人： Kazuhiro Fujikawa

IPC分类号： H02M5/297 ,  H01L29/808 ,  H01L29/812

CPC分类号： H01L29/812 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66901 ,  H01L29/808

摘要： The present invention provides a bi-directional field effect transistor and a matrix converter using the same, in which a current flowing bi-directionally can be controlled by means of a single device.The bi-directional field effect transistor includes: a semiconductor substrate 1; a gate region which is arranged on the semiconductor substrate 1, with a channel parallel to a principal surface of the substrate 1 and a gate electrode 13a for controlling conductance of the channel; a first region which is arranged on a first side of the channel; and a second region which is arranged on a second side of the channel; wherein a forward current which flows from a first electrode 11a of the first region through the channel to a second electrode 12a of the second region and a backward current which flows from the second electrode 12a through the channel to the first electrode 11a can be controlled by a gate voltage applied to the gate electrode 13a.

摘要翻译： 本发明提供一种双向场效应晶体管和使用该双向场效应晶体管的矩阵转换器，其中可以通过单个器件来控制双向流动的电流。 双向场效应晶体管包括：半导体衬底1; 配置在半导体基板1上的栅极区域，平行于基板1的主面的沟道和用于控制沟道电导的栅电极13a; 布置在所述通道的第一侧上的第一区域; 以及布置在所述通道的第二侧上的第二区域; 其中从第一区域的第一电极11a通过沟道流向第二区域的第二电极12a的正向电流和从第二电极12a通过沟道流向第一电极11a的反向电流可以通过 施加到栅电极13a的栅极电压。

公开(公告)号：US20070278540A1

公开(公告)日：2007-12-06

申请号：US11770414

申请日：2007-06-28

申请人： Takashi Hoshino ,  Shin Harada ,  Kazuhiro Fujikawa ,  Satoshi Hatsukawa ,  Kenichi Hirotsu

发明人： Takashi Hoshino ,  Shin Harada ,  Kazuhiro Fujikawa ,  Satoshi Hatsukawa ,  Kenichi Hirotsu

IPC分类号： H01L29/80 ,  H01L21/337

CPC分类号： H01L29/66068 ,  H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/66909 ,  H01L29/8083

摘要： A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion 8. The n-type drift semiconductor portion 3 is placed on a principal surface of the n+ type drain semiconductor portion 2 and has first to fourth regions 3a to 3d extending in a direction intersecting with the principal surface. The p+ type gate semiconductor portion 4 is placed on the first to third regions 3a to 3c of the n-type drift semiconductor portion 3. The n-type channel semiconductor portion 5 is placed along the p+ type gate semiconductor portion 4 and is electrically connected to the fourth region 3d of the n-type drift semiconductor portion 3.

摘要翻译： 根据本发明的垂直JFET1a具有n +型漏极半导体部分2，n型漂移半导体部分3，p +型栅极半导体部分4 ，n型沟道半导体部分5，n + +型源极半导体部分7和ap + +型栅极半导体部分8。 n型漂移半导体部分3放置在n +型漏极半导体部分2的主表面上，并且具有沿与主表面相交的方向延伸的第一至第四区域3至3d 。 p型+ +型栅极半导体部分4放置在n型漂移半导体部分3的第一至第三区域3至3c上。 n型沟道半导体部分5沿着p + +型栅极半导体部分4放置，并与n型漂移半导体部分3的第四区域3d电连接。

公开(公告)号：US08760223B2

公开(公告)日：2014-06-24

申请号：US13490101

申请日：2012-06-06

申请人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Hiroshi Ishioka

发明人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Kazuya Ishioka

IPC分类号： H02M3/07

CPC分类号： H03K17/04123 ,  H03K2217/0036 ,  H03K2217/0045 ,  H03K2217/009

摘要： A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

摘要翻译： 根据一个实施例的开关电路是包括具有输入，输出和公共端子的至少一个半导体开关元件的开关电路，脉冲状信号被施加在输入端和公共端子之间以切换输出和 公共终端 开关电路还包括电容抑制元件部分，其连接在输入和输出端子之间，输入端子公共端子之间以及输出端子和公共端子之间的至少一个。 电容抑制元件部分减小了电容抑制元件部分连接的半导体开关元件的端子之间的寄生电容小于当电容抑制元件部分未以N倍的频率连接时获得的寄生电容（N为 1或更高）与脉冲状信号的时钟频率一样高。

公开(公告)号：US20130157110A1

公开(公告)日：2013-06-20

申请号：US13819172

申请日：2011-08-23

申请人： Suetsugu Kanai ,  Kazuhiro Fujikawa

发明人： Suetsugu Kanai ,  Kazuhiro Fujikawa

IPC分类号： H01M2/34 ,  H01M6/46 ,  H01M2/26

CPC分类号： H01M2/347 ,  H01M2/14 ,  H01M2/18 ,  H01M2/266 ,  H01M6/46 ,  H01M10/0413 ,  H01M10/0427 ,  H01M10/0436 ,  H01M10/0463 ,  H01M10/0525 ,  H01M10/0585 ,  Y02E60/122

摘要： The stacked battery includes a negative electrode (46) and a positive electrode (41). The negative electrode has a negative electrode main portion (50) and a negative electrode lead (52). The positive electrode has a positive electrode main portion (45) and a positive electrode lead (51). In the negative electrode and the positive electrode, the negative electrode main portion and the positive electrode main portion are stacked in a thickness direction with the negative electrode lead and the positive electrode lead extending in different directions as viewed from above. The positive electrode lead is fixed to a positive electrode case. In the positive electrode lead, a break place (X) is provided outside the negative electrode main portion as viewed from above when the negative electrode and the positive electrode are placed on top of each other. The break place (X) is broken when a shock is applied to the electrodes.

摘要翻译： 叠层电池包括负极（46）和正极（41）。 负极具有负极主体部（50）和负极引线（52）。 正极具有正极主体部（45）和正极引线（51）。 在负极和正极中，负极主体部分和正极主体部分沿厚度方向堆叠，负极引线和正极引线沿着从上方观察的不同方向延伸。 正极引线固定在正极壳体上。 在正极引线中，当负极和正极彼此顶部放置时，从负极电极主体的外侧设置断开位置（X）。 当对电极施加冲击时，断点（X）断裂。

公开(公告)号：US20120306288A1

公开(公告)日：2012-12-06

申请号：US13490240

申请日：2012-06-06

申请人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Kazuya Ishioka ,  Hiroshi Ishioka

发明人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Kazuya Ishioka ,  Hiroshi Ishioka

IPC分类号： H01H47/00

CPC分类号： H03K17/04123 ,  H03K2217/0036 ,  H03K2217/0045 ,  Y10T307/747

摘要： A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

摘要翻译： 根据一个实施例的开关电路包括第一至第四半导体开关元件。 脉冲状信号被施加到开关元件的每个输入端子，使得当第一和第四开关元件处于导通（OFF）状态时，剩余的开关元件处于断开（ON）状态。 开关电路包括第一和第二电容元件。 连接在第二半导体开关元件的输出端子和连接在第二半导体开关元件的输入端子和第四半导体开关元件的输出端子之间的第二电容元件之间的第一电容元件具有电容以减小第二半导体开关元件的输出端之间的寄生电容 以与脉冲状信号的时钟频率相同的频率N倍（N为1以上的整数）的第四开关元件和第二开关元件的输入输出端子。

公开(公告)号：US20120037924A1

公开(公告)日：2012-02-16

申请号：US13281901

申请日：2011-10-26

申请人： Kazuhiro Fujikawa ,  Shin Harada

发明人： Kazuhiro Fujikawa ,  Shin Harada

IPC分类号： H01L29/24 ,  H01L29/80

CPC分类号： H01L29/808 ,  H01L29/1608 ,  H01L29/8083

摘要： A junction field-effect transistor (20) comprises an n-type semiconductor layer (1) having a channel region, a buffer layer (3) formed on the channel region and a p+ region (4a, 4b) formed on the buffer layer (3). The concentration of electrons in the buffer layer (3) is lower than the concentration of electrons in the semiconductor layer (1). The concentration of electrons in the buffer layer (3) is preferably not more than one tenth of the concentration of electrons in the semiconductor layer (1). Thus, the threshold voltage can be easily controlled, and saturation current density of a channel can be easily controlled.

摘要翻译： 结场效应晶体管（20）包括具有沟道区的n型半导体层（1），形成在沟道区上的缓冲层（3）和形成在缓冲层上的p +区（4a，4b） 3）。 缓冲层（3）中的电子浓度低于半导体层（1）中的电子浓度。 缓冲层（3）中的电子浓度优选不超过半导体层（1）中的电子浓度的十分之一。 因此，可以容易地控制阈值电压，并且可以容易地控制通道的饱和电流密度。

公开(公告)号：US07759211B2

公开(公告)日：2010-07-20

申请号：US12077825

申请日：2008-03-20

申请人： Kazuhiro Fujikawa ,  Shin Harada

发明人： Kazuhiro Fujikawa ,  Shin Harada

IPC分类号： H01L21/266

CPC分类号： H01L21/266 ,  H01L21/046 ,  H01L21/0465

摘要： There is provided a method of fabricating semiconductor devices that allows ion implantation to be performed at high temperature with ions accelerated with high energy to help to introduce dopant in a semiconductor substrate, in particular a SiC semiconductor substrate, at a selected region to sufficient depth. To achieve this the method includes the steps of: providing the semiconductor substrate at a surface thereof with a mask layer including a polyimide resin film, or a SiO2 film and a thin metal film; and introducing dopant ions.

摘要翻译： 提供一种制造半导体器件的方法，其允许在高温下用高能量加速的离子进行离子注入，以帮助在半导体衬底（特别是SiC半导体衬底）中将掺杂剂在选定的区域引入足够的深度。 为了实现这一点，该方法包括以下步骤：在半导体衬底的表面设置包括聚酰亚胺树脂膜或SiO 2膜和薄金属膜的掩模层; 并引入掺杂离子。

公开(公告)号：US20100123172A1

公开(公告)日：2010-05-20

申请号：US12596958

申请日：2008-10-03

申请人： Kazuhiro Fujikawa ,  Shin Harada

发明人： Kazuhiro Fujikawa ,  Shin Harada

IPC分类号： H01L29/772 ,  H01L29/812 ,  H01L21/338 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/808 ,  H01L21/047 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/812

摘要： A substrate composed of hexagonally crystalline SiC is prepared such that its main surface is in the direction at which the minimum angle between the main surface and a plane perpendicular to the (0001) plane is one degree or less, for example, in the direction at which the minimum angle between the main surface and the [0001] direction, which is perpendicular to the (0001) plane, is one degree or less. A horizontal semiconductor device is formed on one main surface of the substrate prepared by the foregoing method. Thus, it was possible to improve the value of breakdown voltage significantly over the horizontal semiconductor device in which the main surface of the substrate composed of hexagonally crystalline SiC is in the direction along the (0001) direction.

摘要翻译： 制备由六角晶SiC组成的基板，使得其主表面处于主表面与垂直于（0001）面的平面之间的最小角度为1度或更小的方向，例如在 其中主表面与[0001]方向之间的垂直于（0001）面的最小角度为1度以下。 在通过上述方法制备的基板的一个主表面上形成水平半导体器件。 因此，可以显着地提高击穿电压的值，其中由六边形结晶的SiC构成的基板的主表面沿着（0001）方向的方向。