公开(公告)号：US20100015648A1

公开(公告)日：2010-01-21

申请号：US12567860

申请日：2009-09-28

申请人： Jonathan Matthew Barasch ,  Prasad Devarajan ,  Thomas L. Nickolas ,  Kiyoshi Mori

发明人： Jonathan Matthew Barasch ,  Prasad Devarajan ,  Thomas L. Nickolas ,  Kiyoshi Mori

IPC分类号： G01N33/53

CPC分类号： G01N33/6893 ,  G01N2800/347 ,  G01N2800/52

摘要： Methods of assessing the ongoing kidney status in a subject afflicted with chronic renal failure (CRF) by detecting the quantity of Neutrophil Gelatinase-Associated Lipocalin (NGAL) in fluid samples over time is disclosed. NGAL is a small secreted polypeptide that is protease resistant and consequently readily detected in the urine and serum as a result of chronic renal tubule cell injury. Incremental increases in NGAL levels in CRF patients over a prolonged period of time are diagnostic of worsening kidney disease. This increase in NGAL precedes and correlates with other indicators of worsening CRF, such as increased serum creatinine, increased urine protein secretion, and lower glomerular filtration rate (GFR). Proper detection of worsening (or improving, if treatment has been instituted) renal status over time, confirmed by pre- and post-treatment NGAL levels in the patient, can aid the clinical practitioner in designing and/or maintaining a proper treatment regimen to slow or stop the progression of CRF.

摘要翻译： 公开了通过随时间检测流体样品中嗜中性粒细胞明胶酶相关脂质运载蛋白（NGAL）的量来评估患有慢性肾功能衰竭（CRF）的受试者正在进行的肾脏状态的方法。 NGAL是一种小分泌的多肽，其是蛋白酶抗性的，因此由于慢性肾小管细胞损伤在尿液和血清中容易检测到。 长时间的CRF患者NGAL水平的增加增加是肾脏疾病恶化的诊断。 NGAL的这种增加先于CRF恶化的其他指标，如增加血清肌酐，增加尿蛋白分泌，降低肾小球滤过率（GFR）。 通过患者治疗前和治疗后的NGAL水平证实，正确检测恶化（或改善，如果治疗已经建立）肾脏状态，可以帮助临床从业者设计和/或维持适当的治疗方案缓慢 或停止CRF的进展。

公开(公告)号：US20080014644A1

公开(公告)日：2008-01-17

申请号：US11770214

申请日：2007-06-28

申请人： Jonathan BARASCH ,  Prasad Devarajan ,  Thomas Nickolas ,  Kiyoshi Mori

发明人： Jonathan BARASCH ,  Prasad Devarajan ,  Thomas Nickolas ,  Kiyoshi Mori

IPC分类号： G01N33/48

CPC分类号： G01N33/6893 ,  G01N2800/347 ,  G01N2800/52

摘要： A method of assessing the ongoing kidney status of a mammal afflicted with or at risk of developing chronic renal injury or disease, including chronic renal failure (CRF) by detecting the quantity of Neutrophil Gelatinase-Associated Lipocalin (NGAL) in urine, serum or plasma samples at discrete time periods, as well as over time. Incremental increases in NGAL levels in CRF patients over a prolonged period of time are diagnostic of worsening kidney disease. This increase in NGAL precedes and correlates with other indicators of worsening chronic renal disease or CRF, such as increased serum creatinine, increased urine protein secretion, and lower glomerular filtration rate (GFR). Proper detection of worsening (or improving, if treatment has been instituted) renal status over time, confirmed by pre- and post-treatment NGAL levels in the patient, can aid the clinical practitioner in designing and/or maintaining a proper treatment regimen to slow or stop the progression of CRF.

摘要翻译： 通过检测尿液，血清或血浆中的嗜中性粒细胞明胶酶相关脂质运载蛋白（NGAL）的量来评估患有慢性肾损伤或疾病的哺乳动物的正在进行的肾脏状态的方法，包括慢性肾功能衰竭（CRF） 样品在离散的时间段，以及随着时间的推移。 长时间的CRF患者NGAL水平的增加增加是肾脏疾病恶化的诊断。 NGAL的这种增加先于慢性肾病或CRF恶化的其他指标，如血清肌酐升高，尿蛋白分泌增加，肾小球滤过率（GFR）降低。 通过患者治疗前和治疗后的NGAL水平证实，正确检测恶化（或改善，如果治疗已经建立）肾脏状态，可以帮助临床从业者设计和/或维持适当的治疗方案缓慢 或停止CRF的进展。

公开(公告)号：US20060232242A1

公开(公告)日：2006-10-19

申请号：US11386812

申请日：2006-03-23

申请人： Kiyoshi Mori ,  Yasushi Sato

发明人： Kiyoshi Mori ,  Yasushi Sato

IPC分类号： H02J7/00

CPC分类号： H02J7/0052

摘要： A charging apparatus includes a DC-DC converter for stepping down a charging input voltage, and a charging current controller having two input terminals and one output terminal. The input terminals receive a voltage based on a charging current drawn from a voltage stepped down by the DC-DC converter. The voltage at the output terminal serves as a control voltage for controlling the charging current drawn from the stepped-down voltage.

公开(公告)号：US20060192589A1

公开(公告)日：2006-08-31

申请号：US11337595

申请日：2006-01-24

申请人： Yoshimi Okazaki ,  Kiyoshi Mori ,  Hiroyuki Yamazaki

发明人： Yoshimi Okazaki ,  Kiyoshi Mori ,  Hiroyuki Yamazaki

IPC分类号： H03K19/094

CPC分类号： H03K17/08122 ,  H03K17/163

摘要： An inverter apparatus is composed of a power MOSFET having a source/drain connected to an output terminal, and a gate drive circuit driving a gate of the power MOSFET. The gate drive circuit includes a discharging path connected with the gate of the power MOSFET. The discharging path includes a set of serially-connected diodes which are forward-connected in a direction of a discharge current from the gate of the power MOSFET.

公开(公告)号：US06934119B2

公开(公告)日：2005-08-23

申请号：US10049649

申请日：2001-06-26

申请人： Takuro Kohyama ,  Yoshiyuki Ohishi ,  Kiyoshi Mori

发明人： Takuro Kohyama ,  Yoshiyuki Ohishi ,  Kiyoshi Mori

IPC分类号： G11B17/028 ,  G11B17/04 ,  G11B33/12 ,  G11B17/02

CPC分类号： G11B33/121 ,  G11B17/0281 ,  G11B17/043 ,  G11B17/0436

摘要： A disk drive apparatus according to the present invention includes a horizontal guide mechanism and a vertical guide mechanism, which are disposed between a frame (10) and a slider (60) for slidably guiding the slider (60). The horizontal guide mechanism includes an engaging piece (69b) disposed in at least one of the frame (10) and the slider (60) and an engaging hole (24a), which is disposed in the other and is engaged with the engaging piece (69b). One of the frame (10) and the slider (60), in which the engaging piece (69b) is formed, is made of a metallic sheet material while the engaging piece (69b) is formed by bending part of the metallic sheet material.Forming the engaging piece (69b) by bending part of the metallic sheet material in such a manner simplifies the structure of the disk drive apparatus according to the present invention so that the fabrication is facilitated, enabling fabricating cost to be reduced.

摘要翻译： 根据本发明的盘驱动装置包括水平引导机构和垂直引导机构，它们设置在框架（10）和用于可滑动地引导滑块（60）的滑块（60）之间。 水平引导机构包括设置在框架（10）和滑块（60）中的至少一个中的接合件（69b）和接合孔（24a），该接合孔布置在另一个中并与接合部 （69b）。 其中形成有接合片（69b）的框架（10）和滑块（60）之一由金属片材制成，而接合片（69b）通过弯曲金属片的一部分而形成 材料。 通过以这种方式弯曲金属片材的一部分来形成接合片（69b）简化了根据本发明的盘驱动装置的结构，从而便于制造，从而能够降低制造成本。

公开(公告)号：US06624020B2

公开(公告)日：2003-09-23

申请号：US10131479

申请日：2002-04-25

申请人： Kiyoshi Mori

发明人： Kiyoshi Mori

IPC分类号： H01L218242

CPC分类号： H01L27/10811 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/84 ,  H01L28/90

摘要： In a fabrication method of semiconductor device, a storage node connected to one of source/drain regions of an MOS (Metal Oxide Semiconductor) transistor provided at a semiconductor substrate is formed along a trench provided through a silicon nitride film, a BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate) film and a silicon oxide film grown at low temperature. The silicon oxide film grown at low temperature is formed by either atmospheric pressure CVD (chemical vapor deposition) or plasma CVD. Also, a sidewall protection film is formed so as to prevent shorting between adjacent capacitors by growing a film at low temperature. Thus, a semiconductor device of high performance and high reliability can be provided even in a system LSI (Large Scale Integrated circuit) in which a memory circuit and logic circuit are embedded.

公开(公告)号：US06562525B2

公开(公告)日：2003-05-13

申请号：US09843693

申请日：2001-04-30

申请人： Kiyoshi Mori

发明人： Kiyoshi Mori

IPC分类号： G03F900

CPC分类号： G03F1/84

摘要： On the photo mask are drawn product patterns and mask dimension inspection marks to be arranged around the respective product patterns. Each of the mask dimension inspection marks includes a line pattern having a width equal to a line width of the product pattern. Further, each of the mask dimension inspection marks includes a reference pattern that is disposed adjacent to the line pattern. A width of the mask dimension inspection mark is wider than that of the line pattern.

公开(公告)号：US06335236B1

公开(公告)日：2002-01-01

申请号：US09478533

申请日：2000-01-06

申请人： Kiyoshi Mori

发明人： Kiyoshi Mori

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/823443 ,  H01L27/10873

摘要： A manufacturing method of a semiconductor device obtaining performances respectively required in a MOS transistor in semiconductor memories and a MOS transistor in logic devices even in case of manufacturing a system LSI combining the semiconductor memories with the logic devices. Forming silicide films 7 in a logic device region 11 makes it possible to reduce the resistivity of diffusion regions 9 and a conductive film 4 of polysilicon or the like that will serve as an electrode of a resulting MOS transistor. Therefore, the semiconductor devices can be manufactured in which such the MOS transistor can be used as the MOS transistor in the logic devices that is required to operate at high speed and the MOS transistor is also formed in a DRAM or the like where miniaturization is required. Since no alternation is made of the structures of the respective MOS transistors, a semiconductor device whose performance is equivalent to that of the conventional counterpart can be manufactured.

摘要翻译： 即使在将半导体存储器与逻辑器件组合的系统LSI的制造方法中，半导体器件的制造方法也可以在半导体存储器中的MOS晶体管和逻辑器件中的MOS晶体管中分别获得所需的性能。 在逻辑器件区域11中形成硅化物膜7使得可以降低作为所得MOS晶体管的电极的多晶硅等的扩散区域9和导电膜4的电阻率。 因此，可以制造半导体器件，其中这种MOS晶体管可以用作在高速工作所需的逻辑器件中的MOS晶体管，并且MOS晶体管也形成在需要微型化的DRAM等中 。 由于不会改变各个MOS晶体管的结构，所以可以制造其性能与常规对应物的性能相当的半导体器件。

公开(公告)号：US6114205A

公开(公告)日：2000-09-05

申请号：US183040

申请日：1998-10-30

申请人： Kiyoshi Mori

发明人： Kiyoshi Mori

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L29/7827

摘要： A vertical MOS transistor includes an epitaxially formed channel between its lower source/drain region and upper source/drain region, with a gate electrode in a trench hat extends vertically through those regions. A process for forming the vertical MOS transistor implants the substrate to provide the lower source/drain region, then forms an epitaxial layer that provides the channel over the previously formed lower source/drain region. Then, the upper source/drain region is implanted above the lower source/drain A region and epitaxial channel layer, followed by formation of a vertical trench and polysilicon gate. Forming the epitaxial layer over a previously implanted lower source/drain region allows independent control of the resistivity of the lower source/drain region, such that it can have low resistivity, facilitating device symmetry. Also, the epitaxial channel layer has improved doping uniformity over diffusion type channel region, lowering channel length and increasing performance and yield. Finally, the source/drain regions may incorporate two separate dopants to provide an extended region that further minimizes the channel length while providing higher punch through voltage levels and retaining low resistivity.

摘要翻译： 垂直MOS晶体管包括在其下源极/漏极区域和上部源极/漏极区域之间的外延形成的沟道，沟槽帽中的栅极电极垂直延伸穿过那些区域。 用于形成垂直MOS晶体管的工艺将衬底植入以提供下部源极/漏极区域，然后形成在先前形成的下部源极/漏极区域上提供沟道的外延层。 然后，将上源极/漏极区域注入到下部源极/漏极A区域和外延沟道层的上方，随后形成垂直沟槽和多晶硅栅极。 在先前植入的下部源极/漏极区域上形成外延层允许独立控制下部源极/漏极区域的电阻率，使得其可以具有低电阻率，有助于器件对称性。 此外，外延沟道层在扩散型沟道区上具有改善的掺杂均匀性，降低沟道长度并提高性能和产率。 最后，源极/漏极区域可以包含两个单独的掺杂剂以提供扩展区域，其进一步使通道长度最小化，同时提供更高的穿通电压电平并保持低电阻率。

公开(公告)号：US6107106A

公开(公告)日：2000-08-22

申请号：US19296

申请日：1998-02-05

申请人： Kiyoshi Mori

发明人： Kiyoshi Mori

IPC分类号： H01L21/265 ,  H01L21/66 ,  G21K5/00

CPC分类号： H01L22/20 ,  H01L21/2652

摘要： A method of localized control of integrated circuit parameters according to the present invention is used to adjust a the threshold voltage of an integrated circuit by irradiating an inoperable area with a focused ion beam such that the determination of the correct threshold voltage is facilitated without having to refabricate the integrated circuit in its entirety.

摘要翻译： 根据本发明的集成电路参数的局部控制的方法用于通过用聚焦离子束照射不可操作区域来调整集成电路的阈值电压，使得便于确定正确的阈值电压而不必 整体整合集成电路。