公开(公告)号：USRE43229E1

公开(公告)日：2012-03-06

申请号：US12081248

申请日：2008-04-11

申请人： Takayuki Ito ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/8238 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823842

摘要： A semiconductor device manufacturing method having forming first and second insulating gate portions spaced from each other on a semiconductor substrate, selectively implanting the first conductivity type impurity ions to the first gate electrode and a surface layer of the semiconductor substrate adjacent to the first insulating gate portion, selectively implanting the second conductivity type impurity ions to the second gate electrode and the surface layer adjacent to the second insulating gate portion, after implanting the first and second conductivity types impurity ions, pre-annealing at a first substrate temperature, and after the pre-annealing, main-activating for the first and second types impurity ions at a second substrate temperature higher than the first substrate temperature for a treatment period shorter than a period of the pre-annealing.

摘要翻译： 一种半导体器件制造方法，其具有形成在半导体衬底上彼此间隔开的第一和第二绝缘栅极部分，选择性地将第一导电类型杂质离子注入到第一栅电极和与第一绝缘栅极部分相邻的半导体衬底的表面层 在将第一和第二导电类型的杂质离子注入到第二栅极电极和与第二绝缘栅极部分相邻的表面层之后，在第一衬底温度下进行预退火之后，以及在第一衬底温度之后，选择性地将第二导电型杂质离子注入 在第一衬底温度高于第一衬底温度的第二衬底温度下处理短于预退火周期的处理期间，对第一和第二类杂质离子进行主要激活。

公开(公告)号：US07300832B2

公开(公告)日：2007-11-27

申请号：US10867766

申请日：2004-06-16

申请人： Takayuki Ito ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/336

CPC分类号： H01L21/324 ,  H01L21/2686 ,  H01L29/6659

摘要： A method of semiconductor device manufacture provided includes forming a gate insulating layer upon a single crystal semiconductor substrate, forming a gate electrode made from a polycrystal conductive film upon the gate insulating layer, implanting impurity in the gate electrode and in the surface layer of the semiconductor substrate adjacent to or separate from the gate electrode, performing a first heat treatment, and performing a second heat treatment. The first heat treatment performs heat treatment at a temperature that diffuses the impurity implanted mainly in the gate electrode and controls the diffusion of the impurity implanted in the surface layer of the semiconductor substrate. The second heat treatment performs heat treatment at a higher temperature and for a shorter time than the first heat treatment, and at a temperature that activates the impurity implanted in the semiconductor substrate.

摘要翻译： 提供的半导体器件制造方法包括在单晶半导体衬底上形成栅极绝缘层，在栅极绝缘层上形成由多晶导电膜制成的栅电极，在栅电极和半导体表面层中注入杂质 基板，与栅电极相邻或分离，进行第一热处理，进行第二热处理。 第一热处理在扩散主要在栅电极中注入的杂质的温度下进行热处理，并控制注入在半导体衬底的表面层中的杂质的扩散。 第二热处理在比第一热处理更高的温度和更短的时间进行热处理，并且在激活注入在半导体衬底中的杂质的温度下进行热处理。

公开(公告)号：US07091114B2

公开(公告)日：2006-08-15

申请号：US10238642

申请日：2002-09-11

申请人： Takayuki Ito ,  Toshihiko Iinuma ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Toshihiko Iinuma ,  Kyoichi Suguro

IPC分类号： H01L21/425

CPC分类号： H01L29/6653 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2686 ,  H01L29/66575 ,  H01L29/6659

摘要： Disclosed is a method for manufacturing a semiconductor device comprising implanting ions of an impurity element into a semiconductor region, implanting, into the semiconductor region, ions of a predetermined element which is a group IV element or an element having the same conductivity type as the impurity element and larger in mass number than the impurity element, and irradiating a region into which the impurity element and the predetermined element are implanted with light to anneal the region, the light having an emission intensity distribution, a maximum point of the distribution existing in a wavelength region of not more than 600 nm.

公开(公告)号：US20090309133A1

公开(公告)日：2009-12-17

申请号：US12483728

申请日：2009-06-12

申请人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

发明人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

IPC分类号： H01L29/04 ,  H01L21/20

CPC分类号： H01L21/823807 ,  H01L21/2686 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp(21541/T).

摘要翻译： 一种半导体装置的制造方法，其特征在于，在半导体基板的由第一原子构成的表面上形成有与半导体基板的表面的面积为5〜30％的开口率y的开口的开口部; 在所述开口中形成外延层，所述外延层由含有15〜25％的浓度的第二原子的混合晶体构成，所述第二原子的晶格常数不同于所述第一原子的晶格常数; 将杂质离子注入到外延层中; 并在预定温度T下进行活化退火，预定温度T等于或高于1150℃，并且满足y <= 1E-5exp（21541 / T）的关系。

公开(公告)号：US20080268660A1

公开(公告)日：2008-10-30

申请号：US12108589

申请日：2008-04-24

申请人： Takaharu Itani ,  Kenichi Yoshino ,  Takayuki Ito ,  Takashi Kawakami ,  Tetsuya Kugimiya

发明人： Takaharu Itani ,  Kenichi Yoshino ,  Takayuki Ito ,  Takashi Kawakami ,  Tetsuya Kugimiya

IPC分类号： H01L21/02 ,  H01L21/00

CPC分类号： H01L21/02087 ,  H01L21/26513 ,  H01L21/2686 ,  H01L21/67115 ,  H01L29/66575

摘要： A method of manufacturing a semiconductor device that involves a heat treatment of a semiconductor substrate, has removing a superficial layer from an upper surface of an edge part of said semiconductor substrate, a bevel surface of the edge part of said semiconductor substrate and a side surface of the edge part of said semiconductor substrate; and conducting the heat treatment of said semiconductor substrate by irradiating said semiconductor substrate with light having a pulse width of 0.1 milliseconds to 100 milliseconds from a light source after said superficial layer is removed.

摘要翻译： 制造涉及半导体衬底的热处理的半导体器件的方法，从所述半导体衬底的边缘部分的上表面，所述半导体衬底的边缘部分的斜面以及侧表面 的所述半导体衬底的边缘部分; 以及在去除所述表面层之后，从光源照射具有0.1毫秒至100毫微秒的脉冲宽度的光，从而对所述半导体衬底进行热处理。

公开(公告)号：US07902030B2

公开(公告)日：2011-03-08

申请号：US12483728

申请日：2009-06-12

申请人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

发明人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/2686 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp(21541/T).

摘要翻译： 一种半导体装置的制造方法，其特征在于，在半导体基板的由第一原子构成的表面上形成有与半导体基板的表面的面积为5〜30％的开口率y的开口的开口部; 在所述开口中形成外延层，所述外延层由含有15〜25％的浓度的第二原子的混合晶体构成，所述第二原子的晶格常数不同于所述第一原子的晶格常数; 将杂质离子注入到外延层中; 并在预定温度T下进行活化退火，预定温度T等于或高于1150℃，并且满足y＆nlE; 1E-5exp（21541 / T）的关系。

公开(公告)号：US08148717B2

公开(公告)日：2012-04-03

申请号：US12929504

申请日：2011-01-28

申请人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

发明人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

IPC分类号： H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L21/823807 ,  H01L21/2686 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp (21541/T).

摘要翻译： 一种半导体装置的制造方法，其特征在于，在半导体基板的由第一原子构成的表面上形成有与半导体基板的表面的面积为5〜30％的开口率y的开口的开口部; 在所述开口中形成外延层，所述外延层由含有15〜25％的浓度的第二原子的混合晶体构成，所述第二原子的晶格常数不同于所述第一原子的晶格常数; 将杂质离子注入到外延层中; 并在预定温度T下进行活化退火，预定温度T等于或高于1150℃，并且满足y＆nlE; 1E-5exp（21541 / T）的关系。

公开(公告)号：US20110127578A1

公开(公告)日：2011-06-02

申请号：US12929504

申请日：2011-01-28

申请人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

发明人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

IPC分类号： H01L29/12

CPC分类号： H01L21/823807 ,  H01L21/2686 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp (21541/T).

摘要翻译： 一种半导体装置的制造方法，其特征在于，在半导体基板的由第一原子构成的表面上形成有与半导体基板的表面的面积为5〜30％的开口率y的开口的开口部; 在所述开口中形成外延层，所述外延层由含有15〜25％的浓度的第二原子的混合晶体构成，所述第二原子的晶格常数不同于所述第一原子的晶格常数; 将杂质离子注入到外延层中; 并在预定温度T下进行活化退火，预定温度T等于或高于1150℃，并且满足y＆nlE; 1E-5exp（21541 / T）的关系。

公开(公告)号：US11987060B2

公开(公告)日：2024-05-21

申请号：US17902863

申请日：2022-09-04

申请人： Takayuki Ito

发明人： Takayuki Ito

IPC分类号： B41J2/21 ,  B41J3/54

CPC分类号： B41J2/2132 ,  B41J2/2103 ,  B41J3/543

摘要： An image forming apparatus includes a liquid discharge device and processing circuitry. The liquid discharge device includes at least one nozzle group, where N represents an integer, to discharge liquid. The processing circuitry causes the first nozzle group to discharge in a first scan, causes the second nozzle group to discharge in a second scan, and causes the N-th nozzle group to discharge in an N-th scan to form a complete image. The processing circuitry, with respect to an image completion rate indicating a rate of an image formed by each of the first nozzle group to the N-th nozzle group in the complete image, sets the image completion rate of a portion of the first nozzle group adjacent to the second nozzle group in the sub-scanning direction to be not higher than the image completion rate of any one of the second nozzle group to the N-th nozzle group.

公开(公告)号：US20190283447A1

公开(公告)日：2019-09-19

申请号：US16294510

申请日：2019-03-06

申请人： Suguru Yokozawa ,  Takayuki Ito ,  Nobuyuki Satoh ,  Kohtaroh Ikegami ,  Kenta Sasaki

发明人： Suguru Yokozawa ,  Takayuki Ito ,  Nobuyuki Satoh ,  Kohtaroh Ikegami ,  Kenta Sasaki

IPC分类号： B41J2/21 ,  G06T7/00 ,  B41J29/393

摘要： A liquid discharge apparatus includes a liquid discharge head having at least one nozzle array including a plurality of nozzles lined in a nozzle array direction; a two-dimensional image sensor to capture an image formed by the liquid discharge head; and circuitry. The circuitry is configured to divide the nozzles into a plurality of nozzle units; form a pattern including a plurality of unit patterns with liquid discharged from the nozzle units, respectively; and detect a defective nozzle based on a captured image of each of the unit patterns. The unit patterns are arranged in a staggered manner. Each unit pattern is smaller in size than an image capture range of the two-dimensional image sensor. Each unit pattern includes a number of columns of lines extending in a direction perpendicular to the nozzle array direction, and the number of columns is not smaller than twice the number of nozzle arrays.