公开(公告)号：US11442872B2

公开(公告)日：2022-09-13

申请号：US16545949

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata

IPC: G06F12/14 ,  G11C11/406 ,  G11C11/4074 ,  G06F13/16 ,  G11C11/409

Abstract: Techniques described herein are related to protecting at least a portion of data stored in a memory array. A method may include detecting an invalid memory access request based at least in part on the secret key and the identifier and preventing unauthorized access of a memory array by halting an internal refresh of one or more memory cells associated with the memory array in response to detecting the invalid memory access request.

公开(公告)号：US10672496B2

公开(公告)日：2020-06-02

申请号：US15792473

申请日：2017-10-24

Applicant: Micron Technology, Inc.

Inventor： Joshua E. Alzheimer ,  Gary Howe ,  Harish N. Venkata

IPC: G11C29/00 ,  G11C29/10 ,  G11C29/02 ,  G11C29/12 ,  G11C29/16 ,  G11C29/46 ,  G11C29/20

Abstract: A memory device may include a command controller and a memory array with multiple memory cells. The command controller may receive commands to write a data pattern to the memory cells of the memory array. The data pattern may be repeated across multiple cells of the memory array without further input from input/output data lines. Additionally, the memory device may include one or more counters to assist in accessing the memory cells of the memory array.

公开(公告)号：US10535396B2

公开(公告)日：2020-01-14

申请号：US16049576

申请日：2018-07-30

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata

IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/401 ,  G11C7/10 ,  G11C7/08 ,  G11C11/4096

Abstract: Devices and methods include, for a memory device, generating a main input-output line signal on a main input-output line using driving circuitry. The main input-output line is coupled to multiple sensing amplifiers. Each of the sensing amplifiers each locally generate a local data line from the main data line. Each of the sensing amplifiers also includes multiple local sensing amplifiers that are selectively coupled to the generated local data line for overwriting data in the respective local sensing amplifiers.

公开(公告)号：US20200013448A1

公开(公告)日：2020-01-09

申请号：US16557948

申请日：2019-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Harish N. Venkata

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4074

Abstract: Apparatuses and methods for providing power for memory refresh operations are described. An example apparatus includes refresh circuits, a power amplifier, a power circuit, and a power control circuits. The refresh circuits are configured to refresh memory cells of a memory bank. The power amplifier is configured to provide power when activated to the refresh circuits. The power provided by the power amplifier has a first voltage. The power circuit is configured to receive a power supply voltage and to provide power when activated to the refresh circuits. The power provided by the power amplifier has a second voltage. The power control circuit is configured to compare the first voltage and the target voltage and to provide an activation signal to control activation of the power circuit having an active duration based at least in part on the comparison.

公开(公告)号：US10438646B1

公开(公告)日：2019-10-08

申请号：US16027158

申请日：2018-07-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Harish N. Venkata

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4074

Abstract: Apparatuses and methods for providing power for memory refresh operations are described. An example apparatus includes refresh circuits, a power amplifier, a power circuit, and a power control circuits. The refresh circuits are configured to refresh memory cells of a memory bank. The power amplifier is configured to provide power when activated to the refresh circuits. The power provided by the power amplifier has a first voltage. The power circuit is configured to receive a power supply voltage and to provide power when activated to the refresh circuits. The power provided by the power amplifier has a second voltage. The power control circuit is configured to compare the first voltage and the target voltage and to provide an activation signal to control activation of the power circuit having an active duration based at least in part on the comparison.

公开(公告)号：US10403330B1

公开(公告)日：2019-09-03

申请号：US16163720

申请日：2018-10-18

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  Yu-Feng Chen

IPC: G05F1/10 ,  G11C5/14 ,  G06F12/126 ,  G11C7/10 ,  H03K19/20 ,  G06F12/06

Abstract: Memory devices may have internal circuitry that employs voltages higher than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate, internally, higher voltages for operation. The number of available charge pumps in a memory device may be higher than the number used for certain memory operations. Gating circuitry may be used to selectively enable charge pump cores based on power demands that may be associated with a mode of operation and/or a command.

公开(公告)号：US20190221244A1

公开(公告)日：2019-07-18

申请号：US16360685

申请日：2019-03-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/10 ,  G11C11/4096 ,  G11C11/4091

CPC classification number: G11C7/1006 ,  G11C7/1036 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2211/4013

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.

公开(公告)号：US20190122744A1

公开(公告)日：2019-04-25

申请号：US15792473

申请日：2017-10-24

Applicant: Micron Technology, Inc.

Inventor： Joshua E. Alzheimer ,  Gary Howe ,  Harish N. Venkata

IPC: G11C29/10

Abstract: A memory device may include a command controller and a memory array with multiple memory cells. The command controller may receive commands to write a data pattern to the memory cells of the memory array. The data pattern may be repeated across multiple cells of the memory array without further input from input/output data lines.

公开(公告)号：US10181344B1

公开(公告)日：2019-01-15

申请号：US15855485

申请日：2017-12-27

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata

IPC: G11C11/401 ,  G11C11/408 ,  G11C11/4091

Abstract: Devices and methods include, for a memory device, generating a main input-output line signal on a main input-output line using driving circuitry. The main input-output line is coupled to multiple sensing amplifiers. Each of the sensing amplifiers each locally generate a local data line from the main data line. Each of the sensing amplifiers also includes multiple local sensing amplifiers that are selectively coupled to the generated local data line for overwriting data in the respective local sensing amplifiers.

公开(公告)号：US10157659B1

公开(公告)日：2018-12-18

申请号：US15856826

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata

IPC: G11C7/22 ,  G11C11/4074 ,  G11C11/4096 ,  G11C29/52 ,  G06F11/10 ,  H01L27/108

Abstract: A memory device may include one or more memory banks that store digital data. The memory device includes first tri-state driver circuitry that provides a first signal to a first data read/write (DRW) line coupled between write driver circuitry and one or more DQ pads. The first signal is indicative of either a high state or a medium state. The memory device includes second tri-state driver circuitry that provides a second signal to a second data read/write (DRW) line coupled between the write driver circuitry and the one or more DQ pads. The second signal is indicative of either a medium state or a low state. A voltage level of the medium state is between a voltage level of the high state and a voltage level of the low state.