公开(公告)号：US10811061B1

公开(公告)日：2020-10-20

申请号：US16540873

申请日：2019-08-14

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata

IPC: G11C7/00 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4091

Abstract: Memory devices may employ flip-flops with paired transistors in sense amplifying circuitry to sense charges stored in memory cells to perform read and/or activate operations. Sense amplifying circuitry may employ driving devices in driving circuitry to latch the read memory to a high or low voltage. Embodiments include systems and methods that facilitate reduced memory devices with faster memory cell restore by sharing the driving circuitry in different sense amplifying modules. Embodiments may employ switching circuitry in the sense amplifying circuitry to prevent unintentional or faulty readouts.

公开(公告)号：US10529409B2

公开(公告)日：2020-01-07

申请号：US15292941

申请日：2016-10-13

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  Daniel B. Penney

IPC: G11C7/02 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/408

Abstract: The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier.

公开(公告)号：US20190378557A1

公开(公告)日：2019-12-12

申请号：US16549554

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  Daniel B. Penney

IPC: G11C11/4091 ,  G11C11/4093 ,  G11C11/408

Abstract: The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier.

公开(公告)号：US10418123B2

公开(公告)日：2019-09-17

申请号：US16119856

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Guy S. Perry ,  Harish N. Venkata ,  Glen E. Hush

IPC: G11C29/00

Abstract: Apparatuses and methods related to column repair in memory are described. The sensing circuitry of an apparatus can include a first sensing component, a second sensing component, and a third sensing component. The second sensing component can include a defective sense amplifier that is column repaired. The apparatus can include a controller configured to use the sensing circuitry to shift data from the first sensing component to the third sensing component by transferring the data through the second sensing component. The second sensing component can be physically located between the first sensing component and the third sensing component.

公开(公告)号：US10418088B2

公开(公告)日：2019-09-17

申请号：US16193825

申请日：2018-11-16

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata

IPC: G11C7/22 ,  G11C11/4074 ,  G11C11/4096 ,  G11C29/52 ,  G06F11/10 ,  G11C7/10 ,  H01L27/108 ,  G11C29/04

Abstract: A memory device may include one or more memory banks that store digital data. The memory device includes first tri-state driver circuitry that provides a first signal to a first data read/write (DRW) line coupled between write driver circuitry and one or more DQ pads. The first signal is indicative of either a high state or a medium state. The memory device includes second tri-state driver circuitry that provides a second signal to a second data read/write (DRW) line coupled between the write driver circuitry and the one or more DQ pads. The second signal is indicative of either a medium state or a low state. A voltage level of the medium state is between a voltage level of the high state and a voltage level of the low state.

公开(公告)号：US20180374559A1

公开(公告)日：2018-12-27

申请号：US16119856

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Guy S. Perry ,  Harish N. Venkata ,  Glen E. Hush

IPC: G11C29/00

CPC classification number: G11C29/702 ,  G11C29/785 ,  G11C29/81 ,  G11C29/848

Abstract: The present disclosure includes apparatuses and methods related to column repair in memory. An example apparatus can include sensing circuitry. The sensing circuitry can include a first sensing component, a second sensing component, and a third sensing component. The second sensing component can include a defective sense amplifier that is column repaired. The apparatus can include a controller configured to use the sensing circuitry to shift data from the first sensing component to the third sensing component by transferring the data through the second sensing component. The second sensing component can be physically located between the first sensing component and the third sensing component.

公开(公告)号：US10153007B2

公开(公告)日：2018-12-11

申请号：US14944622

申请日：2015-11-18

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  John F. Schreck ,  Mansour Fardad

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/18

Abstract: Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.

公开(公告)号：US20180349052A1

公开(公告)日：2018-12-06

申请号：US16025058

申请日：2018-07-02

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe ,  Harish N. Venkata

IPC: G06F3/06 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/08 ,  G11C17/16

CPC classification number: G11C7/1012 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1036 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C17/16

Abstract: The present disclosure includes apparatuses and methods related to a shift skip. An example apparatus comprises a plurality of sensing circuitries, comprising respective sense amplifiers and respective compute components. A controller is configured to, responsive to a mask data unit associated with a first sensing circuitry having a particular value, cause a data value to be shifted from a second sensing circuitry to a third sensing circuitry without shifting the data value to the first sensing circuitry, wherein the first sensing circuitry is physically located between the second sensing circuitry and the third sensing circuitry.

公开(公告)号：US11031405B2

公开(公告)日：2021-06-08

申请号：US15802016

申请日：2017-11-02

Applicant: Micron Technology, Inc.

Inventor： Mansour Fardad ,  Harish N. Venkata ,  Jeffrey Koelling

IPC: H01L27/108 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4072 ,  G11C29/12 ,  G11C11/406 ,  G11C29/00 ,  G11C11/4097 ,  G11C5/02

Abstract: Various embodiments comprise methods and related apparatuses formed from those methods for placing at least portions of peripheral circuits under a DRAM memory array, where the peripheral circuits are used to control an operation of the DRAM memory array. In an embodiment, a memory apparatus includes a DRAM memory array and at least one peripheral circuit formed under the DRAM memory array, where the at least one peripheral circuit includes at least one circuit type selected from sense amplifiers and sub-word line drivers. Additional apparatuses and methods are also disclosed.

公开(公告)号：US10971214B2

公开(公告)日：2021-04-06

申请号：US16827044

申请日：2020-03-23

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  Daniel B. Penney

IPC: G11C11/00 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/408 ,  G11C7/02

Abstract: The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier.