公开(公告)号：US11675728B2

公开(公告)日：2023-06-13

申请号：US17360994

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F13/42 ,  G06F13/16 ,  G11C8/06 ,  G06F1/08 ,  G11C8/18

CPC classification number: G06F13/4234 ,  G06F1/08 ,  G06F13/1689 ,  G06F13/4282 ,  G11C8/06 ,  G11C8/18

Abstract: Methods, systems, and apparatuses related to configured dual register clock driver (RCD) devices on a single memory subsystem using different configuration information are described. In some examples, configuration of the two RCD devices with different configuration information may include use of a serial data bus to receive and store first RCD configuration data, which is provided to both of the RCD devices to configure one or more parameters of each respective RCD device. One of the RCD devices may receive second configuration data via a command and address bus to independently update the one or more configuration parameters of one of the two RCD devices.

公开(公告)号：US20230014013A1

公开(公告)日：2023-01-19

申请号：US17936048

申请日：2022-09-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G11C8/18 ,  G11C7/22 ,  G11C7/10 ,  G11C8/06

Abstract: A memory subsystem architecture that includes clock signal routing architecture to split a clock signal to support two register clock driver (RCD) devices. The clock signal routing architecture may include clock signal splitter circuit that enables contemporaneous provision of a common clock signal to the two register clock driver devices. The clock signal splitter circuit may have three legs: a first leg to receive the clock signal from an external bus, and two similar legs to route the clock signal to the RCD devices.

公开(公告)号：US20220076721A1

公开(公告)日：2022-03-10

申请号：US17466961

申请日：2021-09-03

Applicant: Micron Technology, Inc.

Inventor： Matthew B. Leslie

IPC: G11C8/18 ,  G11C8/06 ,  G11C7/10 ,  G06F15/173

Abstract: The present disclosure includes apparatuses and methods related to memory topologies. An apparatus may include a first plurality of clam-shell paired memory devices arranged in a star connection topology, each clam-shelled pair of the first plurality of memory devices being coupled by a respective matched branch to a first common command address signal trace. The apparatus may include a second plurality of memory devices coupled to a second common command address signal trace.

公开(公告)号：US20220005512A1

公开(公告)日：2022-01-06

申请号：US17360922

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G11C7/10 ,  H04L25/03

Abstract: Embodiments of the disclosure include signal processing methods to reduce crosstalk between signal lines of a channel bus using feed forward equalizers (FFEs) configured smear pulse response energy transmitted on signal lines of the channel to reduce pulse edge rates. The coefficients for the FFE may be based on crosstalk interference characteristics. Smearing or spreading pulse response energy across a longer time period using a FFE increases inter-symbol interference (ISI). To counter increased inter-symbol interference caused by smearing pulse response energy, receivers configured to recover symbol data transmitted on the channel bus may each include respective decision-feedback equalizers (DFEs) that are configured to filter ISI from transmitted symbols based on previous symbol decisions of the channel. The combination of the FFE configured to smear pulse responses and the DFE to filter ISI may improve data eye quality for recovery of transmitted data on a channel bus when crosstalk dominates noise.

公开(公告)号：US20200272564A1

公开(公告)日：2020-08-27

申请号：US16797571

申请日：2020-02-21

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC: G06F12/06 ,  G11C29/12 ,  G11C11/4093 ,  H01L25/18 ,  H01L25/065

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.