公开(公告)号：US11527508B2

公开(公告)日：2022-12-13

申请号：US17174177

申请日：2021-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: H01L25/065 ,  H01L25/00

Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. Terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. The conductive structures may be included in a redistribution layer (RDL) structure. The RDL structure may have a “U” shape in some embodiments of the disclosure. Each end of the “U” shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). As a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.

公开(公告)号：US20210391305A1

公开(公告)日：2021-12-16

申请号：US17349657

申请日：2021-06-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: H01L25/065 ,  H01L25/18

Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a point of coupling at an intermediate semiconductor device of the group, and the signal is propagated away from the point of coupling over different (e.g., opposite) signal paths to other semiconductor devices of the group. Loading from the point of coupling at the intermediate semiconductor device to other semiconductor devices of a group may be more balanced than, for example, having a point of coupling at semiconductor device at an end of the group (e.g., a lowest semiconductor device of a stack, a highest semiconductor device of the stack, etc.) and providing a signal therefrom. The more balanced topology may reduce a timing difference between when signals arrive at each of the semiconductor devices.

公开(公告)号：US20210318956A1

公开(公告)日：2021-10-14

申请号：US17356906

申请日：2021-06-24

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC: G06F12/06 ,  G11C29/12 ,  G11C11/4093 ,  H01L25/18 ,  H01L25/065 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：US20210280557A1

公开(公告)日：2021-09-09

申请号：US17174177

申请日：2021-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: H01L25/065 ,  H01L25/00

Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. Terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. The conductive structures may be included in a redistribution layer (RDL) structure. The RDL structure may have a “U” shape in some embodiments of the disclosure. Each end of the “U” shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). As a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.

公开(公告)号：US12189996B2

公开(公告)日：2025-01-07

申请号：US18490589

申请日：2023-10-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F3/06 ,  G06F1/04 ,  G06F13/16

Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.

公开(公告)号：US11915791B2

公开(公告)日：2024-02-27

申请号：US17994848

申请日：2022-11-28

Applicant: Micron Technology, Inc.

Inventor： Matthew B. Leslie

IPC: G11C8/18 ,  G06F15/173 ,  G11C7/10 ,  G11C8/06 ,  G11C5/06

CPC classification number: G11C8/18 ,  G06F15/173 ,  G11C5/06 ,  G11C7/1039 ,  G11C8/06

Abstract: The present disclosure includes apparatuses and methods related to memory topologies. An apparatus may include a first plurality of clam-shell paired memory devices arranged in a star connection topology, each clam-shelled pair of the first plurality of memory devices being coupled by a respective matched branch to a first common command address signal trace. The apparatus may include a second plurality of memory devices coupled to a second common command address signal trace.

公开(公告)号：US11862294B2

公开(公告)日：2024-01-02

申请号：US17936048

申请日：2022-09-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C7/22

CPC classification number: G11C8/18 ,  G11C7/1063 ,  G11C7/222 ,  G11C8/06

Abstract: A memory subsystem architecture that includes clock signal routing architecture to split a clock signal to support two register clock driver (RCD) devices. The clock signal routing architecture may include clock signal splitter circuit that enables contemporaneous provision of a common clock signal to the two register clock driver devices. The clock signal splitter circuit may have three legs: a first leg to receive the clock signal from an external bus, and two similar legs to route the clock signal to the RCD devices.

公开(公告)号：US11797229B2

公开(公告)日：2023-10-24

申请号：US17360943

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F3/06 ,  G06F1/04 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F1/04 ,  G06F13/1689 ,  G06F2213/16

Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.

公开(公告)号：US20220005515A1

公开(公告)日：2022-01-06

申请号：US17360964

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G11C8/18 ,  G11C8/06 ,  G11C7/10 ,  G11C7/22

Abstract: A memory subsystem architecture that includes clock signal routing architecture to split a clock signal to support two register clock driver (RCD) devices. The clock signal routing architecture may include clock signal splitter circuit that enables contemporaneous provision of a common clock signal to the two register clock driver devices. The clock signal splitter circuit may have three legs: a first leg to receive the clock signal from an external bus, and two similar legs to route the clock signal to the RCD devices.

公开(公告)号：US20230154512A1

公开(公告)日：2023-05-18

申请号：US17994848

申请日：2022-11-28

Applicant: Micron Technology, Inc.

Inventor： Matthew B. Leslie

IPC: G11C8/18 ,  G06F15/173 ,  G11C7/10 ,  G11C8/06 ,  G11C5/06

CPC classification number: G11C8/18 ,  G06F15/173 ,  G11C7/1039 ,  G11C8/06 ,  G11C5/06

Abstract: The present disclosure includes apparatuses and methods related to memory topologies. An apparatus may include a first plurality of clam-shell paired memory devices arranged in a star connection topology, each clam-shelled pair of the first plurality of memory devices being coupled by a respective matched branch to a first common command address signal trace. The apparatus may include a second plurality of memory devices coupled to a second common command address signal trace.