公开(公告)号：US20230048855A1

公开(公告)日：2023-02-16

申请号：US17884365

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Aliasger T. Zaidy ,  Glen E. Hush ,  Kunal R. Parekh

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.

公开(公告)号：US20220392509A1

公开(公告)日：2022-12-08

申请号：US17846751

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Shivam Swami ,  Sean S. Eilert ,  Ameen D. Akel

IPC: G11C11/22

Abstract: Methods, systems, and devices for memory accessing with auto-precharge are described. For example, a memory system may be configured to support an activate with auto-precharge command, which may be associated with a memory device opening a page of memory cells, latching respective logic states stored by the memory cells at a row buffer, writing logic states back to the page of memory cells, and maintaining the latched logic states at the row buffer (e.g., while maintaining power to latches of the row buffer, after closing the page of memory cells, while the page of memory cells is closed).

公开(公告)号：US20220300437A1

公开(公告)日：2022-09-22

申请号：US17837565

申请日：2022-06-10

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kenneth Marion Curewitz ,  Justin M. Eno

IPC: G06F13/16 ,  G06F9/30

Abstract: A memory chip (e.g., DRAM) connecting a SoC and an accelerator chip (e.g., an AI accelerator chip). A system including the memory chip and the accelerator chip. The system can include the SoC. The memory chip can include first memory cells to store and provide computation input data (e.g., AI computation input data) received from the SoC to be used by the accelerator chip as computation input (e.g., AI computation input). The memory chip can include second memory cells to store and provide first computation output data (e.g., AI computation output data) received from the accelerator chip to be retrieved by the SoC or reused by the accelerator chip as computation input. The memory chip can also include third memory cells to store second computation output data (e.g., non-AI computation output data) related to non-AI tasks received from the SoC to be retrieved by the SoC for non-AI tasks.

公开(公告)号：US20210081324A1

公开(公告)日：2021-03-18

申请号：US16573527

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Justin M. Eno ,  Sean S. Eilert ,  Shivasankar Gunasekaran ,  Hongyu Wang ,  Shivam Swami

IPC: G06F12/1009 ,  G06F12/1027

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.

公开(公告)号：US20210072986A1

公开(公告)日：2021-03-11

申请号：US16717890

申请日：2019-12-17

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Sivagnanam Parthasarathy ,  Shivasankar Gunasekaran ,  Ameen D. Akel

IPC: G06F9/30 ,  G11C7/06 ,  G11C7/10

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-serial way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of the memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

公开(公告)号：US10922020B2

公开(公告)日：2021-02-16

申请号：US16382511

申请日：2019-04-12

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G06F3/06 ,  G11C15/04 ,  G11C13/00

Abstract: An apparatus (e.g., a content addressable memory system) can have a controller, a first content addressable memory coupled to the controller, and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to write data in the first content addressable memory, cause the second content addressable memory to write the data in the second content addressable memory, and cause the second content addressable memory to query the data written in the second content addressable memory while the first content addressable memory continues to write the data in the first content addressable memory.

公开(公告)号：US20200326880A1

公开(公告)日：2020-10-15

申请号：US16382511

申请日：2019-04-12

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G06F3/06 ,  G11C15/04 ,  G11C13/00

Abstract: An apparatus (e.g., a content addressable memory system) can have a controller, a first content addressable memory coupled to the controller, and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to write data in the first content addressable memory, cause the second content addressable memory to write the data in the second content addressable memory, and cause the second content addressable memory to query the data written in the second content addressable memory while the first content addressable memory continues to write the data in the first content addressable memory.

公开(公告)号：US20140281278A1

公开(公告)日：2014-09-18

申请号：US13842984

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth M. Curewitz ,  Sean S. Eilert

IPC: G06F3/06

CPC classification number: G06F3/067 ,  G06F3/061 ,  G06F3/0635

Abstract: Apparatuses and methods for a distributed memory system including memory nodes are disclosed. An example apparatus includes a processor and a memory system coupled to the processor. The memory system is configured to receive instructions from the processor to access information stored by the memory system. The memory system includes a plurality of memory nodes, wherein each memory node of the plurality of memory nodes is coupled to at least one other memory node of the plurality of memory nodes, and each memory node of the plurality of memory nodes is configured to generate an internal message including instructions for an operation, the internal message to be provided to another memory node of the plurality of memory nodes to perform the operation.

Abstract translation: 公开了包括存储器节点的分布式存储器系统的装置和方法。 示例性设备包括处理器和耦合到处理器的存储器系统。 存储器系统被配置为从处理器接收指令以访问由存储器系统存储的信息。 存储器系统包括多个存储器节点，其中多个存储器节点中的每个存储器节点耦合到多个存储器节点中的至少一个其他存储器节点，并且多个存储器节点中的每个存储器节点被配置为产生 包括用于操作的指令的内部消息，所述内部消息将被提供给所述多个存储器节点中的另一存储器节点以执行所述操作。

公开(公告)号：US20250165160A1

公开(公告)日：2025-05-22

申请号：US19033755

申请日：2025-01-22

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Justin Eno ,  Ameen D. Akel

IPC: G06F3/06 ,  H03M13/09 ,  H03M13/11

Abstract: Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

公开(公告)号：US12299291B2

公开(公告)日：2025-05-13

申请号：US17369869

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Justin Eno ,  Ameen D. Akel

IPC: H03M13/11 ,  G06F3/06 ,  H03M13/09

Abstract: Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.