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    MAPPING A VIRTUAL ADDRESS USING A CONTENT ADDRESSABLE MEMORY (CAM)
    35.
    发明申请
    MAPPING A VIRTUAL ADDRESS USING A CONTENT ADDRESSABLE MEMORY (CAM) 有权

    公开(公告)号：US20210365360A1

    公开(公告)日：2021-11-25

    申请号：US17324291

    申请日：2021-05-19

    Applicant: Micron Technology, Inc.

    Inventor： Harold Robert G. Trout ,  Troy D. Larsen ,  Timothy P. Finkbeiner ,  Glen E. Hush ,  Troy A. Manning

    IPC: G06F12/02 ,  G06F12/06 ,  G06F12/1045 ,  G11C15/04

    Abstract: Methods, apparatuses, and systems related to mapping a virtual address using a content addressable memory (CAM) are described. In a memory system including a memory and a content addressable memory (CAM), a select line of the CAM can be coupled to a corresponding select line of the memory, which allows the memory system to map a virtual address of a memory device directly to the corresponding select line of the memory. An example method can include receiving, from a host at a memory device comprising a memory array and a content addressable memory (CAM), a first virtual address to be searched among virtual addresses stored within the CAM, identifying, in response to receipt of the first virtual address, a select line of a plurality of select lines of the CAM associated with a second virtual address matching the first virtual address, and activating, in response to identifying the select line of the CAM, a corresponding select line of the memory coupled to the identified select line of the CAM.

    SORT IN MEMORY USING TABLE SPLITTING
    36.
    发明申请
    SORT IN MEMORY USING TABLE SPLITTING 有权

    公开(公告)号：US20210365205A1

    公开(公告)日：2021-11-25

    申请号：US17324418

    申请日：2021-05-19

    Applicant: Micron Technology, Inc.

    Inventor： Harold Robert G. Trout ,  Troy D. Larsen ,  Timothy P. Finkbeiner ,  Troy A. Manning ,  Glen E. Hush

    IPC: G06F3/06

    Abstract: The present disclosure includes systems, apparatuses and methods related to maintaining data in a sorted order in a memory array to improve access time to data in the memory array and directing access to a row of data in cache based upon an address associated with the data. In a number of embodiments, a number of keys that are stored in a first row of an index table can be split between the first row and a second row in response to the first row being full, where the number of keys are copied to the second row and a first portion of the number of keys remain in the first row and a second portion of the number of keys are moved to the second row.

    SORT IN MEMORY USING INDEX AND KEY TABLES
    37.
    发明申请
    SORT IN MEMORY USING INDEX AND KEY TABLES 有权

    公开(公告)号：US20210365204A1

    公开(公告)日：2021-11-25

    申请号：US17324216

    申请日：2021-05-19

    Applicant: Micron Technology, Inc.

    Inventor： Harold Robert G. Trout ,  Troy D. Larsen ,  Troy A. Manning ,  Timothy P. Finkbeiner ,  Glen E. Hush

    IPC: G06F3/06

    Abstract: The present disclosure includes systems, apparatuses and methods related to maintaining data in a sorted order in a memory array to improve access time to data in the memory array and directing access to a row of data in cache based upon an address associated with the data. In a number of embodiments, data can be sorted by receiving a portion of data for storage in a memory device, extracting a key associated with the portion of data, determining a row of an index table to store the key, and placing the key along with a number of keys in the row of the index table in a sorted order, wherein the sorted order is in relation to keys associated with portions of data previously stored in the memory device.

    SORT IN MEMORY
    38.
    发明申请
    SORT IN MEMORY 有权

    公开(公告)号：US20210365188A1

    公开(公告)日：2021-11-25

    申请号：US17324170

    申请日：2021-05-19

    Applicant: Micron Technology, Inc.

    Inventor： Harold Robert G. Trout ,  Glen E. Hush ,  Troy A. Manning ,  Timothy P. Finkbeiner ,  Troy D. Larsen

    IPC: G06F3/06

    Abstract: The present disclosure includes systems, apparatuses and methods related to maintaining data in a sorted order in a memory array to improve access time to data in the memory array and directing access to a row of data in cache based upon an address associated with the data. In a number of embodiments, data stored in tables in sorted order can allow access to data based on upon the keys and/or the sorted order of the data, which can increase access times to data the memory array.

    COHERENT MEMORY ACCESS
    39.
    发明申请
    COHERENT MEMORY ACCESS 审中-公开

    公开(公告)号：US20200117609A1

    公开(公告)日：2020-04-16

    申请号：US16156654

    申请日：2018-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Timothy P. Finkbeiner ,  Troy D. Larsen

    IPC: G06F12/0877

    Abstract: Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address. Coherent access can be provided using a first cache line address register of the first cache controller which stores the memory address and a second cache line address register of the second cache controller which also stores the memory address.

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