公开(公告)号：US08867262B2

公开(公告)日：2014-10-21

申请号：US13443511

申请日：2012-04-10

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C11/417

CPC分类号： G11C11/417 ,  G11C5/14 ,  G11C5/148

摘要： A semiconductor device includes plural memory cells each having a first inverter and a second inverter, with an input of the first inverter being coupled to an output of the second inverter and an input of the second inverter being coupled to an output of the first inverter. The first and second inverters have drive transistors supplied with a source voltage where the source voltage is raised in response to a level shift of a control signal supplied to a switch of a control circuit. The control circuit further includes a resistance element in parallel with a MOS transistor connected as a diode.

摘要翻译： 半导体器件包括多个具有第一反相器和第二反相器的存储单元，第一反相器的输入端耦合到第二反相器的输出，第二反相器的输入端耦合到第一反相器的输出端。 第一和第二反相器具有供应源电压的驱动晶体管，其中源电压响应于提供给控制电路的开关的控制信号的电平偏移而升高。 控制电路还包括与连接为二极管的MOS晶体管并联的电阻元件。

公开(公告)号：US08493775B2

公开(公告)日：2013-07-23

申请号：US13587900

申请日：2012-08-16

申请人： Masanao Yamaoka ,  Kenichi Osada

发明人： Masanao Yamaoka ,  Kenichi Osada

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C11/412

摘要： The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.

摘要翻译： 半导体器件在用于确定字线激活时间的字线定时信号与参考信号之间进行比较，当比较结果表示读取的低条件时，施加用于放大读取余量的反向栅极偏置 并且当比较结果表示写入余量的低条件时，施加用于扩大写入裕度的反向栅极偏置。 参考信号是根据是否补偿根据字线激活时间（或字线脉冲宽度）而波动的工作裕度，或者根据工艺波动（或阈值电压的变化）来补偿工作裕量波动， 。 通过根据字线脉冲宽度控制背栅极偏压，可以提高根据字线脉冲宽度而波动的工作裕度，以及由于其制造期间的阈值电压的变化而波动的工作裕度。

公开(公告)号：US08350409B2

公开(公告)日：2013-01-08

申请号：US12759520

申请日：2010-04-13

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Yasuhiro Fujimura ,  Tetsuya Fukuoka ,  Ryo Nishino

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Yasuhiro Fujimura ,  Tetsuya Fukuoka ,  Ryo Nishino

IPC分类号： H02J1/10

CPC分类号： G06F1/32 ,  G06F1/3287 ,  Y02D10/171 ,  Y10T307/50

摘要： Objects of the invention are to minimize power consumption while maintaining the required information processing capabilities of an LSI chip by supplying multiple voltages to the LSI chip such that its circuit blocks receive necessary voltages and to prevent an increase in the chip area of the LSI chip and performance degradation of signal wires, which may result from the supply of the multiple voltages, by reducing the number of power supply wires.In an LSI chip to which two voltages are supplied, high voltage wires are more densely spaced than low voltage wires. By selectively applying voltages based on circuit block performance, it is possible to reduce power consumption while maintaining the amount of information processed by the LSI chip.

摘要翻译： 本发明的目的是通过向LSI芯片提供多个电压使得其电路块接收必要的电压并防止LSI芯片的芯片面积的增加来保持LSI芯片所需的信息处理能力，从而最小化功耗，并且 通过减少电源线的数量，可能由多个电压的供给引起的信号线的性能下降。 在提供两个电压的LSI芯片中，高压电线与低压电线相比密度更高。 通过基于电路块性能选择性地施加电压，可以在保持由LSI芯片处理的信息量的同时降低功耗。

公开(公告)号：US08107279B2

公开(公告)日：2012-01-31

申请号：US12563231

申请日：2009-09-21

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

IPC分类号： G11C11/00

CPC分类号： G11C11/417

摘要： High manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS.SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS.SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

摘要翻译： 实现了高制造产量，并补偿了CMOS.SRAM中每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据测定结果分别被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS.SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。

公开(公告)号：US07920438B2

公开(公告)日：2011-04-05

申请号：US12003970

申请日：2008-01-04

申请人： Masanao Yamaoka ,  Kenichi Osada

发明人： Masanao Yamaoka ,  Kenichi Osada

IPC分类号： G11C11/413 ,  G11C11/4193 ,  G11C5/14 ,  G11C7/24

CPC分类号： G11C29/02 ,  G11C5/146 ,  G11C5/147 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

摘要： An SRAM circuit operates at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operating voltage of a memory cell with the operating voltage of a peripheral circuit in order to adjust it to the optimum value, and the substrate bias voltage is further controlled.

摘要翻译： SRAM电路通过增加或优化SRAM电路的工作裕度，以较低的工作电压工作，特别是在低工作电压下工作。 检测SRAM电路中产生的晶体管的阈值电压，以将存储单元的工作电压与外围电路的工作电压进行比较，以将其调整到最佳值，并进一步控制衬底偏置电压。

公开(公告)号：US07596013B2

公开(公告)日：2009-09-29

申请号：US11943495

申请日：2007-11-20

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

IPC分类号： G11C11/00

CPC分类号： G11C11/417

摘要： High manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS•SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

摘要翻译： 实现了高制造产量，并补偿了CMOS.SRAM中每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据测定结果分别被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS.SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。

公开(公告)号：US20090129142A1

公开(公告)日：2009-05-21

申请号：US12357663

申请日：2009-01-22

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Kiyoo Itoh ,  Takayuki Kawahara

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Kiyoo Itoh ,  Takayuki Kawahara

IPC分类号： G11C11/00 ,  H01L27/01

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/108 ,  H01L27/1203 ,  Y10S257/903

摘要： A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.

摘要翻译： SRAM存储器由FD-SOI晶体管组成，通过控制构成驱动晶体管的SOI晶体管的埋入氧化膜下​​的层的电位来提高存储单元的性能。 提高了处于低功率电压状态的SRAM电路的性能。 在由FD-SOI晶体管构成的SRAM存储单元中，控制BOX层下的阱的电位来控制阈值电压Vth，从而增加电流。 因此，可以稳定存储单元的操作。

公开(公告)号：US07333385B2

公开(公告)日：2008-02-19

申请号：US11204024

申请日：2005-08-16

申请人： Masanao Yamaoka ,  Kenichi Osada

发明人： Masanao Yamaoka ,  Kenichi Osada

IPC分类号： G11C5/14 ,  G11C11/4193

CPC分类号： G11C29/02 ,  G11C5/146 ,  G11C5/147 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

摘要： An SRAM circuit operates at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operating voltage of a memory cell with the operating voltage of a peripheral circuit in order to adjust it to the optimum value, and the substrate bias voltage is further controlled.

摘要翻译： SRAM电路通过增加或优化SRAM电路的工作裕度，以较低的工作电压工作，特别是在低工作电压下工作。 检测SRAM电路中产生的晶体管的阈值电压，以将存储单元的工作电压与外围电路的工作电压进行比较，以将其调整到最佳值，并进一步控制衬底偏置电压。

公开(公告)号：US20070159874A1

公开(公告)日：2007-07-12

申请号：US11717629

申请日：2007-03-14

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

IPC分类号： G11C11/00

CPC分类号： G11C11/417 ,  G11C5/14 ,  G11C5/148

摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

公开(公告)号：US20070133260A1

公开(公告)日：2007-06-14

申请号：US11657026

申请日：2007-01-24

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

IPC分类号： G11C11/00

CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。