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    Semiconductor memory
    1.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US07498637B2

    公开(公告)日：2009-03-03

    申请号：US11151455

    申请日：2005-06-14

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Kiyoo Itoh ,  Takayuki Kawahara

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Kiyoo Itoh ,  Takayuki Kawahara

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L27/11 ,  G11C11/00

    CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/108 ,  H01L27/1203 ,  Y10S257/903

    摘要： A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.

    摘要翻译： SRAM存储器由FD-SOI晶体管组成，通过控制构成驱动晶体管的SOI晶体管的埋入氧化膜下​​的层的电位来提高存储单元的性能。 提高了处于低功率电压状态的SRAM电路的性能。 在由FD-SOI晶体管构成的SRAM存储单元中，控制BOX层下的阱的电位来控制阈值电压Vth，从而增加电流。 因此，可以稳定存储单元的操作。

    Semiconductor memory
    2.
    发明申请
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US20050276094A1

    公开(公告)日：2005-12-15

    申请号：US11151455

    申请日：2005-06-14

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Kiyoo Itoh ,  Takayuki Kawahara

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Kiyoo Itoh ,  Takayuki Kawahara

    IPC分类号： G11C11/00 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/108

    CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/108 ,  H01L27/1203 ,  Y10S257/903

    摘要： A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.

    摘要翻译： SRAM存储器由FD-SOI晶体管组成，通过控制构成驱动晶体管的SOI晶体管的埋入氧化膜下​​的层的电位来提高存储单元的性能。 提高了处于低功率电压状态的SRAM电路的性能。 在由FD-SOI晶体管构成的SRAM存储单元中，控制BOX层下的阱的电位来控制阈值电压Vth，从而增加电流。 因此，可以稳定存储单元的操作。

    SEMICONDUCTOR MEMORY
    3.
    发明申请
    SEMICONDUCTOR MEMORY 审中-公开
    半导体存储器

    公开(公告)号：US20090129142A1

    公开(公告)日：2009-05-21

    申请号：US12357663

    申请日：2009-01-22

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Kiyoo Itoh ,  Takayuki Kawahara

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Kiyoo Itoh ,  Takayuki Kawahara

    IPC分类号： G11C11/00 ,  H01L27/01

    CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/108 ,  H01L27/1203 ,  Y10S257/903

    摘要： A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.

    摘要翻译： SRAM存储器由FD-SOI晶体管组成，通过控制构成驱动晶体管的SOI晶体管的埋入氧化膜下​​的层的电位来提高存储单元的性能。 提高了处于低功率电压状态的SRAM电路的性能。 在由FD-SOI晶体管构成的SRAM存储单元中，控制BOX层下的阱的电位来控制阈值电压Vth，从而增加电流。 因此，可以稳定存储单元的操作。

    Semiconductor device formed on a SOI substrate
    4.
    发明申请
    Semiconductor device formed on a SOI substrate 审中-公开
    形成在SOI衬底上的半导体器件

    公开(公告)号：US20070246767A1

    公开(公告)日：2007-10-25

    申请号：US11812694

    申请日：2007-06-21

    申请人： Kenichi Osada ,  Takayuki Kawahara ,  Masanao Yamaoka

    发明人： Kenichi Osada ,  Takayuki Kawahara ,  Masanao Yamaoka

    IPC分类号： H01L29/76

    CPC分类号： H01L29/78648 ,  G11C11/412 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0928 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78609 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate.

    摘要翻译： 完全耗尽型SOI衬底的MISFETS的阈值不能通过改变杂质密度来控制，就像体硅硅MISFET那样。 因此，难以为每个电路设定合适的阈值。 根据本发明的半导体器件，构成存储单元的P沟道型MISFET的栅电极由N型多晶硅制成，N沟道型MISFET的栅电极由P型多晶硅制成，栅电极为P 通道型和外围电路的N沟道型MISFET和逻辑电路由P型硅锗制成。 对于使用SOI衬底的每个电路，可以实现合适的阈值，从而可以充分利用SOI衬底的特性。

    Semiconductor apparatus
    5.
    发明授权
    Semiconductor apparatus 有权
    半导体装置

    公开(公告)号：US08508968B2

    公开(公告)日：2013-08-13

    申请号：US13461848

    申请日：2012-05-02

    申请人： Makoto Saen ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

    发明人： Makoto Saen ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

    IPC分类号： G11C5/06 ,  G11C7/00 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L25/0657 ,  G11C5/02 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

    摘要： The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.

    摘要翻译： 通过采用其中执行一次发送的电路（TR-00T）和用于执行多个接收（TR-10R，TR-20R，TR-30R）的电路的连接拓扑结构来消除对中介操作的需要 连接到一个穿透电极组（例如，TSVGL-0）。 为了实现连接拓扑，即使在堆叠多个LSI的情况下，尤其是用于指定用于发送的各个穿透电极端口或用于接收的可编程存储器元件，以及地址分配 各个贯通电极端口安装在堆叠的LSI中。

    Semiconductor device with speed performance measurement
    7.
    发明授权
    Semiconductor device with speed performance measurement 失效
    具有速度性能测量的半导体器件

    公开(公告)号：US07911221B2

    公开(公告)日：2011-03-22

    申请号：US12335331

    申请日：2008-12-15

    申请人： Masanao Yamaoka ,  Kenichi Osada

    发明人： Masanao Yamaoka ,  Kenichi Osada

    IPC分类号： H03K19/00

    CPC分类号： H03K19/00346

    摘要： A speed performance measurement circuit that may perform speed performance measurement is provided between a first logic circuit and a second logic circuit. The speed performance measurement circuit includes a first flip flop that stores first data, a first delay circuit that delays the first data and generates second data, and a second flip flop that stores the second data. Furthermore, the speed performance measurement circuit includes a first comparator circuit that compares output of the first flip flop to output of the second flip flop, and a third flip flop that stores output data from the first comparator circuit in accordance with timing of the first clock signal. Data in a normal path is compared to data in a path delayed by a certain time to measure speed, and power voltage of a circuit is determined based on such comparison. Thus, change in speed with respect to power voltage in a critical path can be measured.

    摘要翻译： 可以在第一逻辑电路和第二逻辑电路之间提供可执行速度性能测量的速度性能测量电路。 速度性能测量电路包括存储第一数据的第一触发器，延迟第一数据并产生第二数据的第一延迟电路和存储第二数据的第二触发器。 此外，速度性能测量电路包括第一比较器电路，其将第一触发器的输出与第二触发器的输出进行比较;以及第三触发器，其根据第一时钟的定时存储来自第一比较器电路的输出数据 信号。 将正常路径中的数据与延迟一定时间的路径中的数据进行比较以测量速度，并且基于这样的比较确定电路的功率电压。 因此，可以测量关键路径中的功率电压的速度变化。

    Semiconductor memory device with memory cells operated by boosted voltage
    10.
    发明授权
    Semiconductor memory device with memory cells operated by boosted voltage 有权
    具有由升压电压工作的存储单元的半导体存储器件

    公开(公告)号：US07397693B2

    公开(公告)日：2008-07-08

    申请号：US11657026

    申请日：2007-01-24

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    IPC分类号： G11C11/00

    CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

    摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

    摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。