公开(公告)号：US5684809A

公开(公告)日：1997-11-04

申请号：US798848

申请日：1997-02-12

申请人： Eric Stave ,  Phillip G. Wald

发明人： Eric Stave ,  Phillip G. Wald

IPC分类号： G11C29/34 ,  G06F11/00

CPC分类号： G11C29/34

摘要： A test circuit and method for a semiconductor memory array such as a dynamic random access memory (DRAM) or static random access memory (SRAM) array that reduces the required testing time. A row of memory cells is concurrently written to a logic level, then read. Any faulty memory cells will discharge both true and complementary data lines through a diode or a diode-connected FET. The resulting voltage on the data line is less than its precharged high logic level, allowing detection of any faulty memory cell in the row of memory cells.

摘要翻译： 一种用于诸如动态随机存取存储器（DRAM）或静态随机存取存储器（SRAM）阵列的半导体存储器阵列的测试电路和方法，其减少了所需的测试时间。 一行存储单元同时写入逻辑电平，然后读取。 任何有故障的存储单元将通过二极管或二极管连接的FET放电真实和互补的数据线。 数据线上产生的电压小于其预充电高逻辑电平，允许检测存储单元行中的任何故障存储单元。

公开(公告)号：US07366946B2

公开(公告)日：2008-04-29

申请号：US11702809

申请日：2007-02-06

申请人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

发明人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

IPC分类号： G06F11/00

CPC分类号： G11C29/822 ,  G11C11/401 ,  G11C17/14 ,  G11C29/74

摘要： Redundancy in a read only memory (ROM) embedded dynamic random access memory (DRAM) is accomplished by programming redundancy elements such as antifuses or registers with ROM data which is read instead of erroneous data. Multiple identical arrays of ROM bits can also be used for redundancy.

摘要翻译： 只读存储器（ROM）嵌入式动态随机存取存储器（DRAM）中的冗余通过编程冗余元件来实现，诸如反向熔丝或寄存器，ROM数据被读取而不是错误的数据。 多个相同的ROM位阵列也可用于冗余。

公开(公告)号：US07218547B2

公开(公告)日：2007-05-15

申请号：US10843161

申请日：2004-05-11

申请人： Casey Kurth ,  Scott Derner ,  Phillip G. Wald

发明人： Casey Kurth ,  Scott Derner ,  Phillip G. Wald

IPC分类号： G11C11/24

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A ROM embedded DRAM provides ROM cells that can be electrically programmed to a data state using DRAM capacitor memory cells. Numerous techniques for reading the memory cells are provided if a single state memory is desired. For example, bias techniques allow un-programmed ROM cells to be read accurately. In one embodiment, the memory includes program circuitry to short capacitor plates together by breaking down an intermediate dielectric layer using anti-fuse programming techniques.

摘要翻译： ROM嵌入式DRAM提供可以使用DRAM电容器存储单元电可编程为数据状态的ROM单元。 如果需要单个状态存储器，则提供用于读取存储器单元的许多技术。 例如，偏置技术允许未编程的ROM单元被精确地读取。 在一个实施例中，存储器包括通过使用反熔丝编程技术分解中间介电层将电容器板短路在一起的程序电路。

公开(公告)号：US07099212B2

公开(公告)日：2006-08-29

申请号：US10924309

申请日：2004-08-23

申请人： Casey Kurth ,  Scott Derner ,  Phillip G. Wald

发明人： Casey Kurth ,  Scott Derner ,  Phillip G. Wald

IPC分类号： G11C7/00

CPC分类号： H01L27/10844 ,  G11C11/005 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10811 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11293

摘要： A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high substrate leakage. The ROM cells, therefore, are hard programmed to a logic zero state. Bias techniques can be used to read un-programmed ROM cells accurately. As described, sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. A differential pre-charge operation can also be used in another embodiment.

公开(公告)号：US07001816B2

公开(公告)日：2006-02-21

申请号：US10924416

申请日：2004-08-24

申请人： Casey Kurth ,  Scott Derner ,  Phillip G. Wald

发明人： Casey Kurth ,  Scott Derner ,  Phillip G. Wald

IPC分类号： H01L21/336

CPC分类号： H01L27/10844 ,  G11C11/005 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10811 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11293

摘要： A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high substrate leakage. The ROM cells, therefore, are hard programmed to a logic zero state. Bias techniques can be used to read un-programmed ROM cells accurately. As described, sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. A differential pre-charge operation can also be used in another embodiment.

摘要翻译： ROM嵌入式DRAM提供可以编程为单个状态的ROM单元。 ROM单元包括具有存储节点的电容器。 存储节点被处理以具有基本上高的衬底泄漏。 因此，ROM单元硬编程为逻辑0状态。 偏置技术可用于准确读取未编程的ROM单元。 如所描述的，读出放大器电路在一个实施例中可以被偏移到默认为未编程状态。 在另一个实施例中，偏置电路耦合到位线以有利于未编程状态。 差分预充电操作也可以在另一实施例中使用。

公开(公告)号：US06996021B2

公开(公告)日：2006-02-07

申请号：US10899894

申请日：2004-07-27

申请人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

发明人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

IPC分类号： G11C7/02

CPC分类号： G11C7/14 ,  G11C7/06 ,  G11C17/12 ,  G11C17/18 ,  G11C2207/104

摘要： A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. Further, a differential pre-charge operation can also be used in another embodiment. The ROM embedded DRAM allows for simplifier fabrication and programming of the ROM cells, while providing accurate dual state functionality.

公开(公告)号：US06788603B2

公开(公告)日：2004-09-07

申请号：US10376769

申请日：2003-02-28

申请人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

发明人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

IPC分类号： G11C702

CPC分类号： G11C7/14 ,  G11C7/06 ,  G11C17/12 ,  G11C17/18 ,  G11C2207/104

摘要： A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. Further, a differential pre-charge operation can also be used in another embodiment. The ROM embedded DRAM allows for simplifier fabrication and programming of the ROM cells, while providing accurate dual state functionality.

公开(公告)号：US06703326B2

公开(公告)日：2004-03-09

申请号：US10227334

申请日：2002-08-23

申请人： Richard H. Lane ,  Phillip G. Wald

发明人： Richard H. Lane ,  Phillip G. Wald

IPC分类号： H01L2126

CPC分类号： H01L21/28185 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/324 ,  H01L29/513 ,  H01L29/518 ,  Y10S438/904 ,  Y10S438/908

摘要： This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized, sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

摘要翻译： 本发明体现了一种用于退火集成电路以修复制造引起的损伤的改进方法。 集成电路在其中存在包含氢气的形成气体的加压密封室中进行退火。 通过增加氢气到制造集成电路的材料的扩散速率，腔室的加压减小了最终退火步骤对总热暴露的贡献。 理想地，除了氢气之外，形成气体还包含至少一种不与氢气反应的其它气体，例如氮气或氩气，从而降低爆炸危险。 然而，集成电路可以仅包含保持在大于环境大气压的压力的氢气的环境中退火。

公开(公告)号：US06670289B2

公开(公告)日：2003-12-30

申请号：US10150319

申请日：2002-05-17

申请人： Richard H. Lane ,  Phillip G. Wald

发明人： Richard H. Lane ,  Phillip G. Wald

IPC分类号： H01L21475

CPC分类号： H01L21/28185 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/324 ,  H01L29/513 ,  H01L29/518 ,  Y10S438/904 ,  Y10S438/908

摘要： This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized, sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

摘要翻译： 本发明体现了一种用于退火集成电路以修复制造引起的损伤的改进方法。 集成电路在其中存在包含氢气的形成气体的加压密封室中进行退火。 通过增加氢气到制造集成电路的材料的扩散速率，腔室的加压减小了最终退火步骤对总热暴露的贡献。 理想地，除了氢气之外，形成气体还包含至少一种不与氢气反应的其它气体，例如氮气或氩气，从而降低爆炸危险。 然而，集成电路可以仅包含保持在大于环境大气压的压力的氢气的环境中退火。

公开(公告)号：US06455400B1

公开(公告)日：2002-09-24

申请号：US09596237

申请日：2000-06-13

申请人： Keith Smith ,  Phillip G. Wald

发明人： Keith Smith ,  Phillip G. Wald

IPC分类号： H01L2120

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/76877

摘要： In one aspect, the invention includes a semiconductor processing method comprising depositing a silicon layer over a substrate at different deposition temperatures which at least include increasing the deposition temperature through a range of from about 550° C. to about 560° C. In another aspect, the invention includes a semiconductor processing method comprising, in an uninterrupted deposition process, depositing a silicon layer which comprises an essentially amorphous silicon region, an essentially polycrystalline silicon region, and a transition region interconnecting the essentially amorphous silicon region and the essentially polycrystalline silicon region, the essentially amorphous silicon region having an amorphous silicon content which is greater than or equal to about 90 weight percent of a total material of the amorphous silicon region, the essentially polycrystalline silicon region having a polycrystalline silicon content which is greater than or equal to about 90 weight percent of a total material of the polycrystalline silicon region, the transition comprising an amorphous silicon content and a polycrystalline silicon content, the transition region being defined as a region having both a lower amorphous silicon content than the essentially amorphous silicon region and a lower polycrystalline silicon content than the essentially polycrystalline silicon region, the transition region being at least 45 Angstroms thick.

摘要翻译： 在一个方面，本发明包括一种半导体处理方法，包括在不同的沉积温度下在衬底上沉积硅层，所述沉积温度至少包括将沉积温度提高到约550℃至约560℃的范围。另一方面 本发明包括半导体处理方法，其包括在不间断的沉积工艺中沉积硅层，该硅层包括基本上非晶硅区域，基本上多晶硅区域和将基本上非晶硅区域和基本上多晶硅区域互连的过渡区域 ，所述非晶硅区域的非晶硅含量大于或等于所述非晶硅区域的总材料的约90重量％，所述多晶硅区域的多晶硅含量大于或等于约 90重量 所述多晶硅区域的总材料的百分比，所述过渡包括非晶硅含量和多晶硅含量，所述过渡区域被定义为具有比所述基本上非晶硅区域低的非晶硅含量的区域和下部多晶硅 含量大于基本上多晶硅的区域，该过渡区域至少为45埃厚。