公开(公告)号：US20060097776A1

公开(公告)日：2006-05-11

申请号：US11066256

申请日：2005-02-28

申请人： Masaharu Wada

发明人： Masaharu Wada

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  H02M2001/0032 ,  H02M2001/0045 ,  Y02B70/16

摘要： A voltage applying circuit is provided between a DC/DC converter which lowers a first voltage to generate a second voltage and a load circuit to which the second voltage is to be applied. The voltage applying circuit includes a first terminal to which the first voltage is to be applied, a second terminal connected to the load circuit, a plurality of capacitors, and a switch circuit. The switch circuit connects the capacitors in series between the first terminal and a point of a ground voltage, when the load circuit is in a standby state, and connects the capacitors in parallel between the second terminal and the point of the ground voltage, when the load circuit is in an active state.

摘要翻译： 在降低第一电压以产生第二电压的DC / DC转换器和要施加第二电压的负载电路之间提供电压施加电路。 电压施加电路包括要施加第一电压的第一端子，连接到负载电路的第二端子，多个电容器和开关电路。 当负载电路处于待机状态时，开关电路将电容器串联连接在第一端子和接地电压点之间，并且在第二端子与接地电压点之间并联连接电容器时，当 负载电路处于活动状态。

公开(公告)号：US20060038607A1

公开(公告)日：2006-02-23

申请号：US11004864

申请日：2004-12-07

申请人： Masaharu Wada

发明人： Masaharu Wada

IPC分类号： G05F1/10

CPC分类号： H02M3/073 ,  H02M2003/078

摘要： A pump circuit includes first and second transistors connected between an input terminal and an output terminal, and a capacitor which is connected at its one end to the connection node of the first and second transistors. The pump circuit is responsive to control signals applied to the gate electrodes of the first and second transistors and another end of the capacitor to output from the output terminal a second voltage which is approximately equal to a first voltage applied to the input terminal. A back-gate voltage generating circuit which produces a third voltage which is less than the lower one of the first and second voltages. The third voltage is applied to at least the back gate of the second transistor which outputs the second voltage.

摘要翻译： 泵电路包括连接在输入端子和输出端子之间的第一和第二晶体管，以及在其一端连接到第一和第二晶体管的连接节点的电容器。 泵电路响应于施加到第一和第二晶体管的栅电极的控制信号，电容器的另一端从输出端输出大致等于施加到输入端的第一电压的第二电压。 一种产生低于第一和第二电压中的较低电压的第三电压的背栅极电压产生电路。 第三电压被施加到输出第二电压的第二晶体管的至少后栅极。

公开(公告)号：US06333658B1

公开(公告)日：2001-12-25

申请号：US09707791

申请日：2000-11-08

申请人： Hironobu Akita ,  Satoshi Eto ,  Katsuaki Isobe ,  Masaharu Wada ,  Haruki Toda

发明人： Hironobu Akita ,  Satoshi Eto ,  Katsuaki Isobe ,  Masaharu Wada ,  Haruki Toda

IPC分类号： H03H1126

CPC分类号： H03K5/135

摘要： An analog synchronization circuit includes an input buffer which is supplied with an external clock signal, a delay monitor which is supplied with a clock signal output from the input buffer, an output buffer for outputting a clock signal synchronous with the external clock signal and two charge balance delay circuits. The two charge balance delay circuits are equivalent to delay lines in a mirror type delay locked loop. Each charge balance delay circuits operates once in two consecutive cycles of the external clock signal. The two charge balance delay circuits alternately operate and output signals of the charge balance delay circuits are supplied to the output buffer via an OR gate. First and second capacitors are provided in each charge balance delay circuits. A first current source circuit charges the first capacitor for a time equivalent to a delay time of a forward pulse. The second capacitor is charged by a second current source circuit. A comparator compares charge voltages of the first and second capacitors with each other and generates a timing signal when both charge voltages coincide with each other.

摘要翻译： 模拟同步电路包括被提供有外部时钟信号的输入缓冲器，被提供有从输入缓冲器输出的时钟信号的延迟监视器，用于输出与外部时钟信号同步的时钟信号的输出缓冲器和两个充电 平衡延迟电路。 两个电荷平衡延迟电路等效于镜像延迟锁定环路中的延迟线。 每个电荷平衡延迟电路在外部时钟信号的两个连续周期中运行一次。 两个电荷平衡延迟电路交替工作，并且电荷平衡延迟电路的输出信号通过或门提供给输出缓冲器。 在每个电荷平衡延迟电路中提供第一和第二电容器。 第一电流源电路对第一电容器充电等于正向脉冲的延迟时间的时间。 第二电容器由第二电流源电路充电。 比较器将第一和第二电容器的充电电压彼此进行比较，并且当两个充电电压彼此一致时产生定时信号。

公开(公告)号：US06154406A

公开(公告)日：2000-11-28

申请号：US320553

申请日：1999-05-27

申请人： Shinji Miyano ,  Toshimasa Namekawa ,  Masaharu Wada

发明人： Shinji Miyano ,  Toshimasa Namekawa ,  Masaharu Wada

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C11/4087 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/1006 ,  G11C2207/104 ,  G11C2207/229

摘要： Where a first bit line pair comprises a first bit line and a second bit line, a first memory cell is located at an intersection between a selected word line and the first bit line. Where a second bit line pair comprises a third bit line and a fourth bit line, a second memory cell is located at an intersection between the selected word line and the fourth bit line. A data line pair comprises a first data line and a second data line. A first column switch comprises a first transistor connected between the first bit line and the first data line and a second transistor connected between the second bit line and the second data line. A second column switch comprises a third transistor connected between the third bit line and the first data line and a fourth transistor connected between the fourth bit line and the second data line. A column decoder turns on one of the first column switch and the second column switch in a normal-write mode, and turns on both the first column switch and the second column switch in a block-write mode. In the block-write mode, a potential of the first bit line and a potential of the fourth bit line are complementary to each other. Identical data is written to the first memory cell and the second memory cell.

摘要翻译： 在第一位线对包括第一位线和第二位线的情况下，第一存储器单元位于所选字线和第一位线之间的交叉点处。 在第二位线对包括第三位线和第四位线的情况下，第二存储器单元位于所选字线和第四位线之间的交叉点处。 数据线对包括第一数据线和第二数据线。 第一列开关包括连接在第一位线和第一数据线之间的第一晶体管和连接在第二位线和第二数据线之间的第二晶体管。 第二列开关包括连接在第三位线和第一数据线之间的第三晶体管和连接在第四位线和第二数据线之间的第四晶体管。 列解码器以正常写入模式打开第一列开关和第二列开关中的一个，并以块写模式打开第一列开关和第二列开关。 在块写入模式中，第一位线的电位和第四位线的电位彼此互补。 将相同的数据写入第一存储单元和第二存储单元。