公开(公告)号：US09735810B2

公开(公告)日：2017-08-15

申请号：US13519804

申请日：2011-06-02

Applicant: Hironobu Akita

Inventor： Hironobu Akita

IPC: H04L7/04 ,  H04B1/04 ,  H04L7/033 ,  H04L7/00 ,  H04B15/02 ,  H04B15/04

Abstract: A transmitting device has a transmission data generating part and an output buffer part. The transmission data generating part transmits a data and a clock, which are to be transmitted to a receiving device, and outputs them to the output buffer part. The output buffer part includes a data transmitting part and a clock transmitting part. The clock transmitting part generates and transmits a clock intermittently phase-shifted. The data transmitting part transmits the data in sync with the clock transmitted from the clock transmitting part.

公开(公告)号：US09584228B2

公开(公告)日：2017-02-28

申请号：US12747807

申请日：2009-12-09

Applicant: Hironobu Akita

Inventor： Hironobu Akita

IPC: H04B15/04

CPC classification number: H04B15/04 ,  H04B2215/067

Abstract: A transmitter 1 comprises a clock generation portion 4, FIFO portion 6, and serial signal creation portion 7. The clock generation portion 4 performs modulation by spectrum spreading of a reference clock CKref, and generates a first clock CK1 with a high modulation factor and a second clock CK2 with a low modulation factor. The FIFO portion 6 takes as inputs the first clock CK1 which has been output from the clock generation portion 4 to a data generation portion 2 and output from the data generation portion 2, a parallel data signal which has been synchronized with the first clock CK1 in the data generation portion 2 and output, and the second clock CK2 output from the clock generation portion 4, and synchronizes the parallel data signal Pdata with the second clock CK2 and outputs the parallel data signal Pdata. The serial signal creation portion 7 converts a parallel data signal PRdata into a serial data signal Sdata.

Abstract translation: 发射机1包括时钟产生部分4，FIFO部分6和串行信号产生部分7.时钟产生部分4通过参考时钟CKref的频谱扩展执行调制，并产生具有高调制因数的第一时钟CK1和 具有低调制因子的第二时钟CK2。 FIFO部分6将已经从时钟产生部分4输出的第一时钟CK1作为输入，作为数据生成部分2输出，并从数据生成部分2输出与第一时钟CK1同步的并行数据信号 数据产生部分2和从时钟产生部分4输出的第二时钟CK2，并行并行数据信号Pdata与第二时钟CK2并输出并行数据信号Pdata。 串行信号产生部分7将并行数据信号PRdata转换为串行数据信号Sdata。

公开(公告)号：US20100266080A1

公开(公告)日：2010-10-21

申请号：US12808598

申请日：2009-10-27

Applicant: Hironobu Akita ,  Seiichi Ozawa ,  Yohei Ishizone ,  Satoshi Miura

Inventor： Hironobu Akita ,  Seiichi Ozawa ,  Yohei Ishizone ,  Satoshi Miura

IPC: H04L7/04

CPC classification number: H04L7/10 ,  G09G5/008 ,  H03L7/095 ,  H04L7/033 ,  H04L7/046

Abstract: Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication system 1 sends, to the receiving device 3, a serial data signal Sdata that is set as a constant value across a period of a constant multiple of a cycle of the clock when a bit rate of a serial data signal Sdata in the transmission device 2 is changed. The receiving device 3 that received the serial data signal Sdata receives training data Tdata from the transmission device 2 when it is determined that the serial data signal Sdata is a constant value across a period of a constant multiple of a cycle of the clock, and proceeds to the processing of confirming the changed bit rate.

Abstract translation: 提供具有简单配置并能够可靠地执行改变的比特率的确认的传输设备，接收设备和通信系统。 通信系统1向发送装置3发送串行数据信号Sdata，该串行数据信号Sdata在传输中的串行数据信号Sdata的比特率时，在时钟的周期的恒定倍数的周期内被设定为恒定值 设备2更改。 接收到串行数据信号Sdata的接收装置3当确定串行数据信号Sdata在时钟的周期的恒定倍数的周期内是恒定值时，从发送装置2接收训练数据Tdata，并且进行 以确认改变的比特率的处理。

公开(公告)号：US06552357B2

公开(公告)日：2003-04-22

申请号：US10077899

申请日：2002-02-20

Applicant: Hironobu Akita

Inventor： Hironobu Akita

IPC: H01L2906

CPC classification number: H01L27/10897 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/4094

Abstract: A dynamic semiconductor memory device includes memory cells each having a one-transistor/one-capacitor. The memory cells are arranged at their respective intersections of bit lines and word lines. Bit-line precharge circuits are provided at bit line pairs, respectively, to precharge and equalize the bit line pairs. An output potential of a plate potential generator is applied to the power supply terminals of the bit-line precharge circuits. The memory cells have a plurality of capacitors. A plate electrode of the capacitors are connected in common. An insulation film is formed on the plate electrode and a wiring layer is formed on the insulation film. The wiring layer is electrically connected to the plate electrode through a via hole formed in the insulation film and connected in common to the power supply terminals of the bit-line precharge circuits through a contact hole formed in the insulation film, thereby transmitting a potential in proportion to variations in plate potential.

公开(公告)号：US06438059B2

公开(公告)日：2002-08-20

申请号：US09874208

申请日：2001-06-06

Applicant: Hironobu Akita ,  Kenji Tsuchida

Inventor： Hironobu Akita ,  Kenji Tsuchida

IPC: G11C700

CPC classification number: H01L27/0817

Abstract: A fuse is programmed by being supplied with a current. The fuse is connected to a thyristor. A control circuit is connected to the gate of the thyristor. The control circuit turns the thyristor ON to allow the fuse to be programmed.

Abstract translation: 通过提供电流来编程保险丝。 保险丝连接到晶闸管。 控制电路连接到晶闸管的栅极。 控制电路将晶闸管导通，以使熔丝被编程。

公开(公告)号：US6144074A

公开(公告)日：2000-11-07

申请号：US196548

申请日：1998-11-20

Applicant: Hironobu Akita

Inventor： Hironobu Akita

IPC: H01L27/108 ,  H01L21/8242 ,  H01L23/60 ,  H01L23/62 ,  H01L29/00

CPC classification number: H01L27/10894 ,  H01L23/60 ,  H01L23/62 ,  H01L27/10852 ,  H01L2924/0002

Abstract: At least one dummy storage node is formed for a plurality of storage nodes provided in stack type memory cells in which a plate electrode is grounded through the at least one dummy storage node, thereby charges flowed into the plate electrode being discharged, when dry etching is performed by using charged particles, thus preventing electrical stress from acting on a capacitor dielectric film provided between the storage nodes and the plate electrode.

Abstract translation: 为堆叠型存储单元中设置的多个存储节点形成至少一个虚拟存储节点，其中通过至少一个虚拟存储节点对平板电极进行接地，从而当干蚀刻为 通过使用带电粒子进行，从而防止电应力作用在设置在存储节点和平板电极之间的电容器电介质膜上。

公开(公告)号：US09418583B2

公开(公告)日：2016-08-16

申请号：US13517462

申请日：2010-12-13

Applicant: Seiichi Ozawa ,  Hironobu Akita

Inventor： Seiichi Ozawa ,  Hironobu Akita

IPC: G09G5/00 ,  G09G3/20 ,  G09G3/36 ,  H04L25/02

CPC classification number: G09G3/20 ,  G09G3/3611 ,  G09G2300/0426 ,  G09G2310/08 ,  G09G2370/08 ,  H04L25/0264

Abstract: Reception devices 201 to 20N are arranged one-dimensionally in this order. The reception device 20n has a data input buffer 21, a first clock input buffer 221, and a first clock output buffer 231. The first clock input buffer 221 buffers a clock input to the first clock terminals P21 and P22, and outputs it to the first clock output buffer 231. The first clock output buffer 231 buffers a clock input from the first clock input buffer 221 and outputs it from the second clock terminals P31 and P32. The data input terminals P11 and P12 are located between the first clock terminal and the second clock terminal.

Abstract translation: 接收装置201〜20N依次排列成一维。 接收装置20n具有数据输入缓冲器21，第一时钟输入缓冲器221和第一时钟输出缓冲器231.第一时钟输入缓冲器221缓冲输入到第一时钟端子P21和P22的时钟，并将其输出到 第一时钟输出缓冲器231缓冲从第一时钟输入缓冲器221输入的时钟并将其从第二时钟端子P31和P32输出。 数据输入端子P11和P12位于第一时钟端子和第二时钟端子之间。

公开(公告)号：US06608514B1

公开(公告)日：2003-08-19

申请号：US09511352

申请日：2000-02-23

Applicant: Hironobu Akita ,  Katsuaki Isobe ,  Masaharu Wada ,  Kenji Tsuchida ,  Haruki Toda

Inventor： Hironobu Akita ,  Katsuaki Isobe ,  Masaharu Wada ,  Kenji Tsuchida ,  Haruki Toda

IPC: H03K300

CPC classification number: G11C7/222 ,  G11C7/22 ,  H03K5/00006 ,  H03K5/135

Abstract: A clock signal generator circuit comprises an off-chip driver, a first clock control circuit for outputting a first internal clock signal Tu synchronizing with an external clock signal CK, a second clock control circuit for outputting a second internal clock signal Td 180° out-of-phase with the external clock signal CK, a third clock control circuit for outputting a third internal clock signal aTx1 synchronizing with the first clock signal Tu and advanced in phase by at least the signal delay time in the off-chip driver, a fourth clock control circuit for outputting a fourth internal clock signal aTx2 synchronizing with the second clock signal Td and advanced in phase by at least the signal delay time in the off-chip driver, an OR circuit to which the third and fourth internal clock signals aTx1, aTx2 are inputted and which outputs a fifth internal clock signal aTx, and a fifth clock control circuit for outputting a sixth internal clock signal Tx which is in synchronization with the fifth internal clock signal aTx outputted from the OR circuit, has twice the frequency of the external clock signal CK, and is advanced in phase by the signal delay time in the off-chip driver.

Abstract translation: 时钟信号发生器电路包括片外驱动器，用于输出与外部时钟信号CK同步的第一内部时钟信号Tu的第一时钟控制电路，用于将第二内部时钟信号Td 180°输出的第二时钟控制电路， 与外部时钟信号CK的同相;第三时钟控制电路，用于输出与第一时钟信号Tu同步的第三内部时钟信号aTx1并至少在芯片外驱动器中的信号延迟时间相位前进;第四时钟控制电路， 时钟控制电路，用于输出与第二时钟信号Td同步的第四内部时钟信号aTx2并至少在片外驱动器中的信号延迟时间相位前进;第三和第四内部时钟信号aTx1， 输入aTx2并输出第五内部时钟信号aTx，以及第五时钟控制电路，用于输出与f同步的第六内部时钟信号Tx 从OR电路输出的第四内部时钟信号aTx具有外部时钟信号CK的两倍频率，并且在片外驱动器中相位提前信号延迟时间。

公开(公告)号：US06449212B1

公开(公告)日：2002-09-10

申请号：US09628449

申请日：2000-07-28

Applicant: Haruki Toda ,  Hironobu Akita ,  Katsuaki Isobe

Inventor： Haruki Toda ,  Hironobu Akita ,  Katsuaki Isobe

IPC: G11C800

CPC classification number: H03L7/00 ,  H03K5/08 ,  H03K5/13 ,  H03K5/135

Abstract: A first capacitor is charged by a constant current source circuit for a time corresponding to the delay time of forward pulses. A second capacitor is charged by a constant current source circuit. A comparator compares the voltages of the first and second capacitors, and outputs a timing signal when these voltages match. For this reason, a timing at which the second capacitor has been charged for a time corresponding to the delay time of backward pulses can be obtained.

Abstract translation: 第一电容器由恒流源电路充电一段与正向脉冲的延迟时间对应的时间。 第二电容器由恒流源电路充电。 比较器比较第一和第二电容器的电压，并且当这些电压匹配时输出定时信号。 因此，可以获得第二电容器已经对与反向脉冲的延迟时间相对应的时间的定时。

公开(公告)号：US06362999B1

公开(公告)日：2002-03-26

申请号：US09772069

申请日：2001-01-30

Applicant: Hironobu Akita ,  Shinichiro Shiratake ,  Fumihiro Kohno

Inventor： Hironobu Akita ,  Shinichiro Shiratake ,  Fumihiro Kohno

IPC: G11C506

Abstract: The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.