公开(公告)号：US20070023759A1

公开(公告)日：2007-02-01

申请号：US11469748

申请日：2006-09-01

申请人： Masato Hiramatsu ,  Masakiyo Matsumura ,  Mikihiko Nishitani ,  Yoshinobu Kimura ,  Yoshitaka Yamamoto

发明人： Masato Hiramatsu ,  Masakiyo Matsumura ,  Mikihiko Nishitani ,  Yoshinobu Kimura ,  Yoshitaka Yamamoto

IPC分类号： H01L29/00

CPC分类号： H01L29/78696 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675

摘要： A thin film transistor includes a one conductive type semiconductor layer (11); a source region (12) and a drain region (13) which are separately provided in the semiconductor layer; and a gate electrode (14) provided above or below the semiconductor layer with an insulating film interposed therebetween, wherein the width (Ws) of the junction face between the source region and the channel (16) which is provided between the source region and drain region, is different from the width (Wd) of the junction face between the above channel region and the drain region.

摘要翻译： 薄膜晶体管包括一个导电型半导体层（11）; 源区域（12）和漏极区域（13），其分开设置在所述半导体层中; 以及设置在所述半导体层的上方或下方的绝缘膜的栅极电极，其中，所述源极区域与所述沟道（16）之间的所述接合面的宽度（W SUB） 设置在源极区域和漏极区域之间，不同于上述沟道区域和漏极区域之间的接合面的宽度（W SUB）。

公开(公告)号：US20050161738A1

公开(公告)日：2005-07-28

申请号：US10508818

申请日：2003-03-04

申请人： Masato Hiramatsu ,  Masakiyo Matsumura ,  Mikihiko Nishitani ,  Yoshinobu Kimura ,  Yoshitaka Yamamoto

发明人： Masato Hiramatsu ,  Masakiyo Matsumura ,  Mikihiko Nishitani ,  Yoshinobu Kimura ,  Yoshitaka Yamamoto

IPC分类号： H01L21/336 ,  H01L21/77 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786 ,  H01L27/01 ,  H01L21/00

CPC分类号： H01L29/78696 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675

摘要： A thin film transistor includes a one conductive type semiconductor layer; a source region and a drain region which are separately provided in the semiconductor layer; and a gate electrode provided above or below the semiconductor layer with an insulating film interposed therebetween, wherein the width of the junction face between the source region and the channel which is provided between the source region and drain region, is different from the width of the junction face between the above channel region and the drain region.

摘要翻译： 薄膜晶体管包括一个导电型半导体层; 源极区和漏极区，分别设置在半导体层中; 以及设置在所述半导体层的上方或下方的绝缘膜的栅电极，其中，所述源极区域与设置在所述源极区域与漏极区域之间的所述沟道的接合面的宽度不同于 在上述沟道区域和漏极区域之间的接合面。

公开(公告)号：US07608891B2

公开(公告)日：2009-10-27

申请号：US11469748

申请日：2006-09-01

申请人： Masato Hiramatsu ,  Masakiyo Matsumura ,  Mikihiko Nishitani ,  Yoshinobu Kimura ,  Yoshitaka Yamamoto

发明人： Masato Hiramatsu ,  Masakiyo Matsumura ,  Mikihiko Nishitani ,  Yoshinobu Kimura ,  Yoshitaka Yamamoto

IPC分类号： H01L27/01

CPC分类号： H01L29/78696 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675

摘要： A thin film transistor includes a one conductive type semiconductor layer (11); a source region (12) and a drain region (13) which are separately provided in the semiconductor layer; and a gate electrode (14) provided above or below the semiconductor layer with an insulating film interposed therebetween, wherein the width (Ws) of the junction face between the source region and the channel (16) which is provided between the source region and drain region, is different from the width (Wd) of the junction face between the above channel region and the drain region.

摘要翻译： 薄膜晶体管包括一个导电型半导体层（11）; 源区域（12）和漏极区域（13），其分开设置在所述半导体层中; 和设置在半导体层的上方或下方的绝缘膜的栅电极（14），其中源极区域和沟道（16）之间的接合面的宽度（Ws）设置在源区域和漏极之间 区域与上述沟道区域和漏极区域之间的接合面的宽度（Wd）不同。

公开(公告)号：US06987035B2

公开(公告)日：2006-01-17

申请号：US10857941

申请日：2004-06-02

申请人： Yoshitaka Yamamoto ,  Mikihiko Nishitani ,  Masato Hiramatsu ,  Masayuki Jyumonji ,  Yoshinobu Kimura

发明人： Yoshitaka Yamamoto ,  Mikihiko Nishitani ,  Masato Hiramatsu ,  Masayuki Jyumonji ,  Yoshinobu Kimura

IPC分类号： H01L21/00

CPC分类号： H01L21/02686 ,  H01L21/2026 ,  H01L29/66772

摘要： A method for forming a crystallized semiconductor layer includes preparing a non-single-crystal semiconductor layer in which at least one crystal seed is formed, and irradiating with an energy ray the non-single-crystal semiconductor layer having the crystal seed formed therein to allow a crystal to laterally grow from the crystal seed in the non-single-crystal semiconductor layer, irradiation of the energy ray is carried out by positioning to at least a part of the crystal seed an area having a minimum intensity value of the energy ray, the energy ray having a confirmation that an area having a maximum intensity value of the energy ray is continuously reduced to the area having the minimum intensity value in an irradiated surface.

摘要翻译： 一种形成结晶化半导体层的方法包括制备其中形成至少一个晶种的非单晶半导体层，并且用能量线照射其中形成晶种的非单晶半导体层以允许 在非单晶半导体层中从晶种横向生长的晶体，通过将至少一部分晶种定位到晶种的至少一部分，进行能量射线的最小强度值的区域的照射， 能量射线确认具有能量射线的最大强度值的区域连续地减少到照射表面中具有最小强度值的区域。

公开(公告)号：US08018154B2

公开(公告)日：2011-09-13

申请号：US12297200

申请日：2007-04-27

申请人： Yusuke Fukui ,  Takuji Tsujita ,  Jun Hashimoto ,  Hikaru Nishitani ,  Masaharu Terauchi ,  Mikihiko Nishitani

发明人： Yusuke Fukui ,  Takuji Tsujita ,  Jun Hashimoto ,  Hikaru Nishitani ,  Masaharu Terauchi ,  Mikihiko Nishitani

IPC分类号： H01J17/49

CPC分类号： H01J11/40 ,  H01J9/02 ,  H01J11/12 ,  H01J11/38

摘要： A PDP can be driven at low voltage while having a charge retention property in a protection layer, and has favorable image display properties. Additionally, the PDP prevents the occurrence of discharge delay and realizes high-quality image display by performing favorable high-speed driving in a high definition PDP. To achieve this, a surface layer (8) is formed to a film thickness of 1 μm in an oxygen atmosphere having an oxygen partial pressure of 0.025 Pa or more, the surface layer (8) is provided on a face of a dielectric layer (7) on a discharge space side. Furthermore, MgO particles (16) are dispersed on a surface of the surface layer (8). The surface layer (8) has the effects of protecting the dielectric layer (7) from ion bombardment during discharge, reducing the firing voltage, and preventing excessive electron loss. Also, the MgO particles (16) have a high initial electron emission property.

摘要翻译： PDP可以在低电压下驱动，同时在保护层中具有电荷保持性，并且具有良好的图像显示性能。 此外，PDP通过在高清晰度PDP中执行有利的高速驱动来防止放电延迟的发生并实现高质量的图像显示。 为了实现这一点，在氧分压为0.025Pa以上的氧气氛中，表面层（8）形成为1μm的膜厚，表面层（8）设置在电介质层的表面（ 7）放电空间侧。 此外，MgO颗粒（16）分散在表面层（8）的表面上。 表面层（8）具有在放电期间保护电介质层（7）免受离子轰击的作用，降低了点火电压，并防止了电子损失过量。 此外，MgO粒子（16）具有高的初始电子发射特性。

公开(公告)号：US07932676B2

公开(公告)日：2011-04-26

申请号：US12680053

申请日：2009-07-16

申请人： Mikihiko Nishitani ,  Masahiro Sakai ,  Yusuke Fukui ,  Yosuke Honda ,  Yasuhiro Yamauchi ,  Michiko Okafuji

发明人： Mikihiko Nishitani ,  Masahiro Sakai ,  Yusuke Fukui ,  Yosuke Honda ,  Yasuhiro Yamauchi ,  Michiko Okafuji

IPC分类号： H01J17/49

CPC分类号： H01J11/12 ,  H01J11/40

摘要： The present invention provides a plasma display panel (PDP) with a protective film improved so as to achieve a lower discharge starting voltage. A surface portion of the protective film 16 substantially is composed of magnesium (Mg), aluminum (Al), nitrogen (N), and oxygen (O). The protective film 16 is formed so that in the surface portion of the protective film 16, a ratio of the number of atoms of the aluminum to a total of the number of atoms of the magnesium and the number of atoms of the aluminum is at least 2.1% but not more than 66.5%, a ratio of the number of atoms of the nitrogen to a total of the number of atoms of the nitrogen and the number of atoms of the oxygen is at least 1.2% but not more than 17.2%, and a ratio of the total of the number of atoms of the nitrogen and the number of atoms of the oxygen to the total of the number of atoms of the magnesium and the number of atoms of the aluminum is at least 1.0 but not more than 1.35.

摘要翻译： 本发明提供一种具有改进的保护膜的等离子体显示面板（PDP），以实现较低的放电起始电压。 保护膜16的表面部分基本上由镁（Mg），铝（Al），氮（N）和氧（O）组成。 保护膜16形成为使得在保护膜16的表面部分中，铝的原子数与镁的原子数与铝的原子数之比至少为 2.1％，但不超过66.5％，氮原子数与氮原子数和氧原子数之比为至少1.2％但不高于17.2％ 并且氮的原子数与氧原子的总数与镁的原子总数和铝的原子数之比为1.0以上1.35以下 。

公开(公告)号：US20100039033A1

公开(公告)日：2010-02-18

申请号：US12015310

申请日：2008-01-16

申请人： Yukihiro Morita ,  Masatoshi Kitagawa ,  Kiichiro Oishi ,  Mikihiko Nishitani

发明人： Yukihiro Morita ,  Masatoshi Kitagawa ,  Kiichiro Oishi ,  Mikihiko Nishitani

IPC分类号： H01J17/49 ,  H01J9/24

CPC分类号： H01J11/40 ,  H01J9/02 ,  H01J11/12

摘要： A plasma display panel in which a first substrate having a protective layer formed thereon opposes a second substrate across a discharge space, with the substrates being sealed around a perimeter thereof. At a surface of the protective layer, first and second materials of different electron emission properties are exposed to the discharge space, with at least one of the materials existing in a dispersed state. The first and second materials may be first and second crystals, and the second crystal may be dispersed throughout the first crystal.

摘要翻译： 一种等离子体显示面板，其中形成有保护层的第一基板横跨放电空间与第二基板相对，基板围绕其周边被密封。 在保护层的表面上，具有不同电子发射特性的第一和第二材料暴露于放电空间，其中至少一种材料以分散状态存在。 第一和第二材料可以是第一和第二晶体，并且第二晶体可以分散在整个第一晶体中。

公开(公告)号：US20080315768A1

公开(公告)日：2008-12-25

申请号：US11572900

申请日：2005-08-11

申请人： Hiroyuki Yamakita ,  Masatoshi Kitagawa ,  Mikihiko Nishitani

发明人： Hiroyuki Yamakita ,  Masatoshi Kitagawa ,  Mikihiko Nishitani

IPC分类号： H01J17/49 ,  H01J9/26

CPC分类号： H01J11/24 ,  H01J9/02 ,  H01J11/12 ,  H01J11/38 ,  H01J2211/245 ,  H01J2211/323

摘要： A PDP (101) with a reduced discharge inception voltage and discharge sustaining voltage for improving luminous efficiency has at least a pair of substrates (110 and 111) that are disposed in opposition to sandwich a discharge space therebetween. At least a portion of at least one of the substrates has two or more display electrode pairs (104) that include narrow bus electrodes (159 and 169), a dielectric layer (107) formed so as to cover the display electrode pairs (104), and a protective layer (108) formed so as to cover the dielectric layer (107). The dielectric layer (107) has a dense film structure with a dielectric breakdown voltage of 1.0×106 [V/cm] to 1.0×107 [V/cm].

摘要翻译： 具有降低的放电起始电压和放电维持电压以提高发光效率的PDP（101）具有至少一对基板（110和111），所述基板相对于其间夹着放电空间设置。 至少一个基板的至少一部分具有两个或更多个显示电极对（104），其包括窄的总线电极（159和169），形成为覆盖显示电极对（104）的电介质层（107） ，和形成为覆盖电介质层（107）的保护层（108）。 电介质层（107）具有介电击穿电压为1.0×10 6 [V / cm]至1.0×10 7 [V / cm]的致密膜结构。

公开(公告)号：US20080278074A1

公开(公告)日：2008-11-13

申请号：US10594294

申请日：2005-04-07

申请人： Shinichi Yamamoto ,  Mikihiko Nishitani ,  Masaharu Terauchi ,  Jun Hashimoto ,  Masatoshi Kitagawa

发明人： Shinichi Yamamoto ,  Mikihiko Nishitani ,  Masaharu Terauchi ,  Jun Hashimoto ,  Masatoshi Kitagawa

IPC分类号： H01J17/49 ,  H01J9/02

CPC分类号： H01J11/12 ,  H01J11/40

摘要： Provided is a gas discharge display panel that exhibits a favorable display performance by maintaining a wall charge retaining power, controlling discharge delay within a range adequate for optimal image display, and reducing the discharge starting voltage at comparatively low cost. Also provided is a PDP that exhibits more reliability with enhanced display quality by further improving the secondary electron emission factor γ compared to conventional cases and lowering the discharge starting voltage to widen the driving margin. Further provided is a manufacturing method of a gas discharge display panel, by which the manufacturing cost lowers by reduction of the exhaustion time in the sealing exhaustion process, and by which the driving circuit cost is reduced. In a gas discharge display panel of the present invention, a protective layer (15) has a first protective film (151) and a second protective film (152), the second protective film (152) is formed on at least part of a surface of the first protective film (151), and the first protective film (151) has a larger impurity content than the second protective film (152).

摘要翻译： 提供一种气体放电显示面板，其通过保持壁电荷保持功率而显示良好的显示性能，将放电延迟控制在适于最佳图像显示的范围内，并且以相对低的成本降低放电启动电压。 还提供了一种PDP，其通过与常规情况相比进一步改善二次电子发射因子γ并降低放电起始电压以扩大驱动裕度，显示出具有增强的显示质量的更高的可靠性。 进一步提供一种气体放电显示面板的制造方法，通过减少密封耗尽处理中的耗尽时间，降低制造成本，降低驱动电路成本。 在本发明的气体放电显示面板中，保护层（15）具有第一保护膜（151）和第二保护膜（152），第二保护膜（152）形成在表面的至少一部分上 的第一保护膜（151），并且第一保护膜（151）的杂质含量比第二保护膜（152）大。

公开(公告)号：US20080157672A1

公开(公告)日：2008-07-03

申请号：US11965554

申请日：2007-12-27

申请人： Takuji Tsujita ,  Yusuke Fukui ,  Masaharu Terauchi ,  Mikihiko Nishitani ,  Michiko Okafuji ,  Shinichiro Ishino ,  Kaname Mizokami

发明人： Takuji Tsujita ,  Yusuke Fukui ,  Masaharu Terauchi ,  Mikihiko Nishitani ,  Michiko Okafuji ,  Shinichiro Ishino ,  Kaname Mizokami

IPC分类号： H01J17/49

CPC分类号： H01J11/40 ,  H01J11/12

摘要： Disclosed is a PDP and a manufacturing method therefor having improved display performance even if the PDP is of a fine-cell structure. A protective layer of the PDP is composed of an MgO film layer and an MgO particle layer that is made of MgO particles. The MgO particles are formed by burning an MgO precursor and satisfy that a/b≧1, where a denotes a spectrum integral value in a wavelength region of a CL spectrum from 200 nm to 300 nm, exclusive of 300 nm, and b denotes a spectrum integral value in a wavelength region of the CL spectrum from 300 nm to 550 nm, exclusive of 550 nm. With provision of the MgO particle layer, the discharge characteristics of the protective layer improve (shorter discharge delay and less temperature dependence of the discharge delay). Consequently, the PDP is ensured to exhibit excellent display performance.

摘要翻译： 公开了即使PDP是细小结构的PDP也具有提高显示性能的制造方法。 PDP的保护层由MgO膜层和由MgO粒子构成的MgO粒子层构成。 通过烧成MgO前体，满足a / b> = 1来形成MgO粒子，其中a表示在200nm至300nm的CL谱的波长区域中的光谱积分值，不包括300nm，b表示 在300nm至550nm的CL光谱的波长区域中的光谱积分值，不包括550nm。 通过提供MgO颗粒层，保护层的放电特性提高（放电延迟更短，放电延迟的温度依赖性较小）。 因此，确保了表现出优异的显示性能的PDP。