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    Error Logging for a Memory Device with On-Die Wear Leveling
    31.
    发明申请
    Error Logging for a Memory Device with On-Die Wear Leveling 有权

    公开(公告)号：US20250085867A1

    公开(公告)日：2025-03-13

    申请号：US18955719

    申请日：2024-11-21

    Applicant: Micron Technology, Inc.

    Inventor： Bryan David Kerstetter ,  Donald M. Morgan ,  Alan J. Wilson ,  John David Porter ,  Jeffrey P. Wright

    IPC: G06F3/06

    Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

    Error logging for a memory device with on-die wear leveling
    32.
    发明授权
    Error logging for a memory device with on-die wear leveling 有权

    公开(公告)号：US12159039B2

    公开(公告)日：2024-12-03

    申请号：US17731100

    申请日：2022-04-27

    Applicant: Micron Technology, Inc.

    Inventor： Bryan David Kerstetter ,  Donald M. Morgan ,  Alan J. Wilson ,  John David Porter ,  Jeffrey P. Wright

    IPC: G06F3/06

    Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

    MEMORY MANAGEMENT HOLDING LATCH PLACEMENT AND CONTROL SIGNAL GENERATION
    33.
    发明公开
    MEMORY MANAGEMENT HOLDING LATCH PLACEMENT AND CONTROL SIGNAL GENERATION 审中-公开

    公开(公告)号：US20240362114A1

    公开(公告)日：2024-10-31

    申请号：US18607152

    申请日：2024-03-15

    Applicant: Micron Technology, Inc.

    Inventor： Jaeil Kim ,  Donald M. Morgan ,  Alan J. Wilson

    IPC: G06F11/10

    CPC classification number: G06F11/1068 ,  G06F11/1016

    Abstract: A system for providing memory management holding latch placement and control signal generation is disclosed. The system performs memory management operations on a memory device to reduce memory cell wear and tear and to balance use of the memory cells of the memory device. The system separates memory management read operations from memory management write operations by utilizing a holding register that stores data from a source memory cell prior to transfer to a target memory cell. When a memory management read operation is initiated, data and error correction parity bits from the source memory cell are provided to a circuit including the holding register. The data and parity bits are analyzed for errors and the errors are corrected prior to storing the data and parity bits into the holding register. The data and associated parity bits are then transferred from the holding register to the target memory cell.

    APPARATUSES AND METHODS FOR SKETCH CIRCUITS FOR REFRESH BINNING
    34.
    发明申请
    APPARATUSES AND METHODS FOR SKETCH CIRCUITS FOR REFRESH BINNING 有权

    公开(公告)号：US20220293166A1

    公开(公告)日：2022-09-15

    申请号：US17201941

    申请日：2021-03-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Sujeet Ayyapureddi ,  Donald M. Morgan

    IPC: G11C11/406 ,  G11C11/408 ,  G11C29/44 ,  G11C29/42

    Abstract: Apparatuses, systems, and methods for sketch circuits for refresh binning. The rows of a memory may have different information retention times. The row addresses may be sorted into different bins based on these information retention times. In order to store information about which row addresses are associated with which bins a sketch circuit may be used. When an address is generated as part of a refresh operation, it may be used to generate a number of different hash values, which may be used to index entries in a storage structure. The entries may indicate which bin the address is associated with. Based on the binning information, the memory may refresh the address at different rates (e.g., by determining whether to provide the address as a refresh address or not).

    Apparatuses and methods for tracking row accesses
    35.
    发明授权
    Apparatuses and methods for tracking row accesses 有权

    公开(公告)号：US11386946B2

    公开(公告)日：2022-07-12

    申请号：US16513400

    申请日：2019-07-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Sujeet Ayyapureddi ,  Donald M. Morgan

    IPC: G11C11/406 ,  G06F9/30 ,  G11C16/34 ,  G11C11/16

    Abstract: Apparatuses and methods for tracking all row accesses in a memory device over time may be used to identify rows which are being hammered so that ‘victim’ rows may be identified and refreshed. A register stack may include a number of count values, each of which may track a number of accesses to a portion of the word lines of the memory device. Anytime a row within a given portion is accessed, the associated count value may be incremented. When a count value exceeds a first threshold, a second stack with a second number of count values may be used to track numbers of accesses to sub-portions of the given portion. When a second count value exceeds a second threshold, victim addresses may be provided to refresh the victim word lines associated with any of the word lines within the sub-portion.

    Memory system including data obfuscation
    37.
    发明授权
    Memory system including data obfuscation 有权

    公开(公告)号：US11093588B2

    公开(公告)日：2021-08-17

    申请号：US15633045

    申请日：2017-06-26

    Applicant: Micron Technology, Inc.

    Inventor： Donald M. Morgan ,  Joseph C. Sher

    IPC: G06F21/14 ,  G06F12/14 ,  G06F21/62

    Abstract: Data obfuscation is generally discussed herein. In one or more embodiments, a memory circuit can include a storage portion including entries with corresponding addresses, one or more of the entries configured to include data stored thereon, and processing circuitry to read first data from a first entry of the entries, alter the first data by at least one of: (1) flipping one or more bits of the first data, (2) scrambling two or more bits of the first data, and (3) altering an address of the first data, and write the altered first data to the storage portion.

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