公开(公告)号：US20240345957A1

公开(公告)日：2024-10-17

申请号：US18751020

申请日：2024-06-21

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/0837 ,  G06F9/38 ,  G06F11/14 ,  G06F12/1009 ,  G06F12/1027 ,  G06N3/02

CPC classification number: G06F12/0837 ,  G06F9/3877 ,  G06F11/1448 ,  G06F12/1009 ,  G06F12/1027 ,  G06N3/02

Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.

公开(公告)号：US11954042B2

公开(公告)日：2024-04-09

申请号：US17943739

申请日：2022-09-13

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/00 ,  G06F12/10 ,  H04L67/1097 ,  H04W84/04

CPC classification number: G06F12/10 ,  H04L67/1097 ,  G06F2212/154 ,  G06F2212/657 ,  H04W84/042

Abstract: Systems, methods and apparatuses of distributed computing based on memory as a service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.

公开(公告)号：US11755884B2

公开(公告)日：2023-09-12

申请号：US16545813

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Sean Stephen Eilert ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Hongyu Wang

IPC: G06N3/04 ,  G06N3/045 ,  G06N20/20 ,  G06N3/048

CPC classification number: G06N3/045 ,  G06N3/048 ,  G06N20/20

Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN). In the system, changes to local versions of the ANN can be combined with a master version of the ANN. In the system, a first device can include memory that can store the master version, a second device can include memory that can store a local version of the ANN, and there can be many devices that store local versions of the ANN. The second device (or any other device of the system hosting a local version) can include a processor that can train the local version, and a transceiver that can transmit changes to the local version generated from the training. The first device can include a transceiver that can receive the changes to a local version, and a processing device that can combine the received changes with the master version.

公开(公告)号：US20230236747A1

公开(公告)日：2023-07-27

申请号：US18190669

申请日：2023-03-27

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Hongyu Wang ,  Justin M. Eno ,  Shivam Swami ,  Samuel E. Bradshaw

IPC: G06F3/06 ,  G06F12/1027

CPC classification number: G06F3/0631 ,  G06F3/0673 ,  G06F3/0607 ,  G06F12/1027

Abstract: A computer system stores metadata that is used to identify physical memory devices that store randomly-accessible data for memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. Stored metadata associates a first address range of the address space with a first memory device, and a second address range of the address space with a second memory device. The operating system manages processes running on the computer system by accessing the stored metadata. This management includes allocating memory based on the stored metadata so that data for a first process is stored in the first memory device, and data for a second process is stored in the second memory device.

公开(公告)号：US20230046808A1

公开(公告)日：2023-02-16

申请号：US17975364

申请日：2022-10-27

Applicant: Micron Technology, Inc.

Inventor： Shivam Swami ,  Kenneth Marion Curewitz

IPC: G06F3/06 ,  G06F12/0804

Abstract: Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task. In response to determining that the performance capability is adequate, the controller changes a mode of operation of the memory system so that one or more resources of the second memory device are used to service the task.

公开(公告)号：US11481334B2

公开(公告)日：2022-10-25

申请号：US17319002

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/00 ,  G06F12/10 ,  H04L67/1097 ,  H04W84/04

Abstract: Systems, methods and apparatuses of distributed computing based on Memory as a Service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.

公开(公告)号：US20220237039A1

公开(公告)日：2022-07-28

申请号：US17723846

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Sean Stephen Eilert ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Dmitri Yudanov

IPC: G06F9/50 ,  H04L41/0896 ,  G06F12/02 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/08 ,  G06F12/1072 ,  G06F12/1036

Abstract: Systems, methods and apparatuses to throttle network communications for memory as a service are described. For example, a computing device can borrow an amount of random access memory of the lender device over a communication connection between the lender device and the computing device. The computing device can allocate virtual memory to applications running in the computing device, and configure at least a portion of the virtual memory to be hosted on the amount of memory loaned by the lender device to the computing device. The computing device can throttle data communications used by memory regions in accessing the amount of memory over the communication connection according to the criticality levels of the contents stored in the memory regions.

公开(公告)号：US11269780B2

公开(公告)日：2022-03-08

申请号：US16573541

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Sean S. Eilert ,  Hongyu Wang ,  Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Justin M. Eno ,  Shivam Swami

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/1027

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).

公开(公告)号：US20210081353A1

公开(公告)日：2021-03-18

申请号：US16573795

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Justin M. Eno ,  Kenneth Marion Curewitz ,  Sean S. Eilert

IPC: G06F15/78 ,  G06F9/30

Abstract: An accelerator chip, e.g., an artificial intelligence (AI) accelerator chip, that can connect a system on a chip (SoC) and a memory chip. The accelerator chip can have a first set of pins configured to connect to the memory chip via wiring, as well as a second set of pins configured to connect to the SoC via wiring. The accelerator chip can be configured to perform and accelerate application-specific computations (e.g., AI computations) for the SoC, as well as use the memory chip as memory for the application-specific computations. For example, the accelerator chip can be an AI accelerator chip and the AI accelerator chip can be configured to perform and accelerate AI computations for the SoC, as well as use the memory chip as memory for the AI computations.

公开(公告)号：US20210081337A1

公开(公告)日：2021-03-18

申请号：US16573805

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kenneth Marion Curewitz ,  Justin M. Eno

IPC: G06F13/16 ,  G06F9/30

Abstract: A memory chip (e.g., DRAM) connecting a SoC and an accelerator chip (e.g., an AI accelerator chip). A system including the memory chip and the accelerator chip. The system can include the SoC. The memory chip can include first memory cells to store and provide computation input data (e.g., AI computation input data) received from the SoC to be used by the accelerator chip as computation input (e.g., AI computation input). The memory chip can include second memory cells to store and provide first computation output data (e.g., AI computation output data) received from the accelerator chip to be retrieved by the SoC or reused by the accelerator chip as computation input. The memory chip can also include third memory cells to store second computation output data (e.g., non-AI computation output data) related to non-AI tasks received from the SoC to be retrieved by the SoC for non-AI tasks.