公开(公告)号：US5805012A

公开(公告)日：1998-09-08

申请号：US653438

申请日：1996-05-24

申请人： Byung-Gil Jeon ,  Chul-Sung Park

发明人： Byung-Gil Jeon ,  Chul-Sung Park

IPC分类号： G11C11/417 ,  G11C5/14 ,  H01L21/8234 ,  H01L27/06 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/08 ,  H03K17/14

CPC分类号： H03K19/00384

摘要： The speed gap between rise and fall times of a buffer biased by a power supply having a power supply voltage, the speed gap varying in a first manner with respect to the power supply voltage and in a second manner inverse to the first manner with respect to a bias current supplied to the buffer, is controlled by generating the bias current such that the bias current varies inversely with respect to the power supply voltage, thereby compensating for fluctuations in the power supply voltage and maintaining the speed gap within a predetermined range when the power supply voltage is greater than a power supply voltage threshold level. The buffer may include a bias transistor controlling the bias current, with the bias current controlled by regulating the differential voltage applied to a control electrode of the bias transistor with an inverse voltage regulator including a control voltage generator for generating a control voltage varying directly with respect to the power supply voltage when the power supply voltage is less than the power supply voltage threshold level and remaining at a control voltage set point level when the power supply voltage is greater than the power supply voltage threshold level, a current feedback regulator for varying the feedback current directly with respect to the power supply voltage, and an output voltage generator for generating the differential voltage from the feedback current and the control voltage such that when the control voltage is at the control voltage set point level, the differential voltage varies inversely with respect to the feedback current.

摘要翻译： 由具有电源电压的电源偏置的缓冲器的上升和下降时间之间的速度差，相对于电源电压以第一种方式变化的速度间隙，以与第一种方式相反的第二种方式相对于 通过产生偏置电流来控制提供给缓冲器的偏置电流，使得偏置电流相对于电源电压反向变化，从而补偿电源电压的波动并且将速度间隙保持在预定范围内，当 电源电压大于电源电压阈值电平。 缓冲器可以包括控制偏置电流的偏置晶体管，偏置电流通过利用包括用于产生直接变化的控制电压的控制电压发生器的反向电压调节器调节施加到偏置晶体管的控制电极的差分电压来控制， 当电源电压小于电源电压阈值电平并且当电源电压大于电源电压阈值电平时保持在控制电压设定点电平时，提供电源电压;电流反馈调节器，用于改变电源电压 反馈电流直接相对于电源电压，以及输出电压发生器，用于从反馈电流和控制电压产生差分电压，使得当控制电压处于控制电压设定点电平时，差分电压与 尊重反馈电流。

公开(公告)号：US07345945B2

公开(公告)日：2008-03-18

申请号：US11232170

申请日：2005-09-21

申请人： Byung-Gil Jeon ,  Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C8/14

摘要： A semiconductor memory device having a word line driver circuit configured in stages. A plurality of sub word line driver circuits are connected, in parallel, to each main word line, and provide a sub word line enable signal to a selected sub word line in response to a main word line enable signal provided through a main word line. A plurality of (local) word line driver circuits are connected in parallel, to each sub word line and provide a local word line enable signal to a selected local word line in response to the (main/sub) word line enable signal so as to operate a plurality of memory cells connected to the selected local word line. The transistor count and layout area of a semiconductor memory device decreases and a reduced chip area can be achieved.

摘要翻译： 具有分级配置的字线驱动电路的半导体存储装置。 多个子字线驱动器电路并联连接到每个主字线，并且响应于通过主字线提供的主字线使能信号，向所选择的子字线提供子字线使能信号。 多个（本地）字线驱动电路并联连接到每个子字线，并响应于（主/副）字线使能信号而向所选择的本地字线提供本地字线使能信号，以便 操作连接到所选择的本地字线的多个存储器单元。 半导体存储器件的晶体管数量和布局面积减小，芯片面积减小。

公开(公告)号：US07221616B2

公开(公告)日：2007-05-22

申请号：US11154621

申请日：2005-06-16

申请人： Byung-Gil Jeon

发明人： Byung-Gil Jeon

IPC分类号： G11C8/00

CPC分类号： G11C11/22 ,  G11C8/08

摘要： Disclosed is a word line driver circuit and a driving method thereof. An input to the circuit has a ground voltage level during a non-selected operating mode and, as the output signal of a word line decoding circuit, is applied at a power source voltage level during a selected operating mode. The output of the circuit has a ground voltage level during the non-selected operating mode and applies a higher voltage than the power source voltage to a word line connected to a memory cell during the selected operating mode. Optionally, a capacitor boosts the output voltage during the selected operating mode.

摘要翻译： 公开了一种字线驱动电路及其驱动方法。 在未选择的操作模式期间，电路的输入具有接地电压电平，并且作为字线解码电路的输出信号在所选择的操作模式期间以电源电压电平施加。 在所选择的操作模式期间，电路的输出具有接地电压电平，并且在所选择的操作模式期间向连接到存储器单元的字线施加比电源电压更高的电压。 可选地，电容器在所选择的操作模式期间提高输出电压。

公开(公告)号：US20070035983A1

公开(公告)日：2007-02-15

申请号：US11484280

申请日：2006-07-11

申请人： Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A FeRAM device and a writing section control method therefor, in which the device includes a memory cell constructed of one access transistor and one ferroelectric capacitor; and a writing control circuit for controlling a first writing section to write data of a first logic state in the memory cell and a second writing section to write data of a second logic state different from the first logic state, in response to an external clock signal. Thus a stabilized write operation can be performed and a reliability of data stored in the memory cell can be tested.

摘要翻译： 一种FeRAM器件及其写入部分控制方法，其中该器件包括由一个存取晶体管和一个铁电电容器构成的存储单元; 以及写入控制电路，用于响应于外部时钟信号，控制第一写入部分将存储单元中的第一逻辑状态的数据写入第二写入部分以写入与第一逻辑状态不同的第二逻辑状态的数据 。 因此，可以执行稳定的写入操作，并且可以测试存储在存储单元中的数据的可靠性。

公开(公告)号：US07173844B2

公开(公告)日：2007-02-06

申请号：US11197033

申请日：2005-08-04

申请人： Han-Joo Lee ,  Kang-Woon Lee ,  Byung-Jun Min ,  Byung-Gil Jeon

发明人： Han-Joo Lee ,  Kang-Woon Lee ,  Byung-Jun Min ,  Byung-Gil Jeon

IPC分类号： G11C11/22

CPC分类号： G11C7/04 ,  G11C5/147 ,  G11C11/22

摘要： A reference voltage generating device that provides a constant reference voltage even with temperature change in a ferroelectric random access memory and a method for driving the same are provided. A device for generating a reference voltage in a ferroelectric random access memory including memory cells, each of which has one ferroelectric capacitor and one access transistor, includes a reference cell composed of a ferroelectric capacitor and a transistor; a reference plate line connected to one end of the ferroelectric capacitor constituting the reference cell; and a reference plate line driver circuit for adjusting a voltage level of a reference plate line enable signal depending on temperature change so that a constant reference voltage is generated.

摘要翻译： 提供了即使在铁电随机存取存储器中的温度变化也提供恒定参考电压的参考电压产生装置及其驱动方法。 一种用于在具有一个铁电电容器和一个存取晶体管的存储单元的铁电随机存取存储器中产生参考电压的装置包括由铁电电容器和晶体管构成的参考电池; 连接到构成参考电池的铁电电容器的一端的参考板线; 以及用于根据温度变化调整参考板线使能信号的电压电平的参考板线驱动电路，从而产生恒定的参考电压。

公开(公告)号：US20060028890A1

公开(公告)日：2006-02-09

申请号：US11197033

申请日：2005-08-04

申请人： Han-Joo Lee ,  Kang-Woon Lee ,  Byung-Jun Min ,  Byung-Gil Jeon

发明人： Han-Joo Lee ,  Kang-Woon Lee ,  Byung-Jun Min ,  Byung-Gil Jeon

IPC分类号： G11C7/02 ,  G11C11/22

CPC分类号： G11C7/04 ,  G11C5/147 ,  G11C11/22

摘要： A reference voltage generating device that provides a constant reference voltage even with temperature change in a ferroelectric random access memory and a method for driving the same are provided. A device for generating a reference voltage in a ferroelectric random access memory including memory cells, each of which has one ferroelectric capacitor and one access transistor, includes a reference cell composed of a ferroelectric capacitor and a transistor; a reference plate line connected to one end of the ferroelectric capacitor constituting the reference cell; and a reference plate line driver circuit for adjusting a voltage level of a reference plate line enable signal depending on temperature change so that a constant reference voltage is generated.

摘要翻译： 提供了即使在铁电随机存取存储器中的温度变化也提供恒定参考电压的参考电压产生装置及其驱动方法。 一种用于在具有一个铁电电容器和一个存取晶体管的存储单元的铁电随机存取存储器中产生参考电压的装置包括由铁电电容器和晶体管构成的参考电池; 连接到构成参考电池的铁电电容器的一端的参考板线; 以及用于根据温度变化调整参考板线使能信号的电压电平的参考板线驱动电路，从而产生恒定的参考电压。

公开(公告)号：US20050128782A1

公开(公告)日：2005-06-16

申请号：US11014117

申请日：2004-12-15

申请人： Byung-Gil Jeon

发明人： Byung-Gil Jeon

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： We describe and claim a ferroelectric memory device includes a plurality of memory cells, each memory cell comprising a ferroelectric capacitor and a transistor, a plate line drive unit capable of providing a first voltage to the memory cell array in response to a plate line drive signal, and a reference voltage generating device. The reference voltage generating includes a reference cell block having a plurality of reference cells, each reference cell including a ferroelectric capacitor and a transistor, and a reference plate line drive to provide a reference plate line voltage to at least one reference cell in response to a plate line drive signal and a reference voltage generation signal, where each reference cell generates a reference voltage in response to the reference plate line voltage.

摘要翻译： 我们描述并要求具有多个存储单元的铁电存储器件，每个存储单元包括铁电电容器和晶体管，板线驱动单元能够响应于板线驱动信号而向存储单元阵列提供第一电压 ，以及参考电压产生装置。 参考电压产生包括具有多个参考单元的参考单元块，每个参考单元包括铁电电容器和晶体管，以及参考板线驱动器，用于响应于至少一个参考单元向基准单元提供参考板线电压 板线驱动信号和参考电压产生信号，其中每个参考单元响应于参考板线电压产生参考电压。

公开(公告)号：US06201727B1

公开(公告)日：2001-03-13

申请号：US09591810

申请日：2000-06-12

申请人： Byung-Gil Jeon

发明人： Byung-Gil Jeon

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： Disclosed herein is a ferroelectric random access memory device that includes a word line, a plate line corresponding to the word line, a plurality of bit lines, and a plurality of memory cells arranged at intersections of the word line and the bit lines. A first NMOS transistor couples and decouples one end of the plate line to the word line responsive to a first switch control signal. A second NMOS transistor couples or decouples the other end of the plate line to a reference voltage responsive to a second switch control signal.

摘要翻译： 本文公开了一种铁电随机存取存储器件，其包括字线，对应于字线的板线，多个位线以及布置在字线和位线的交点处的多个存储单元。 响应于第一开关控制信号，第一NMOS晶体管将板线的一端耦合到字线。 第二NMOS晶体管响应于第二开关控制信号将板线的另一端耦合或去耦合到参考电压。

公开(公告)号：US5991188A

公开(公告)日：1999-11-23

申请号：US84390

申请日：1998-05-27

申请人： Yeon-Bae Chung ,  Byung-Gil Jeon

发明人： Yeon-Bae Chung ,  Byung-Gil Jeon

IPC分类号： G11C14/00 ,  G11C7/00 ,  G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric memory device with plate line segments free from the capacitive plate line segment coupling in a read/write operation, and a method of accessing the memory device. The memory device includes a floating protection circuit for protecting unselected plate line segments from being floated during a read/write operations. The floating protection circuit prevents data disturbance due to the capacitive plate line segment coupling. In a data write method of the memory device, a sense amplifier corresponding to a bit line is activated after a voltage corresponding to a data bit to the bit line is applied. In a data read method of the memory device, the sense amplifier is activated and then a column gate corresponding to the bit line is selected.

摘要翻译： 具有在读/写操作中没有电容板线段耦合的板线段的铁电存储器件以及访问存储器件的方法。 存储器件包括用于在读/写操作期间保护未选择的板线段不浮动的浮动保护电路。 浮动保护电路可防止电容板线段耦合引起的数据干扰。 在存储器件的数据写入方法中，对应于位线的读出放大器在与位线的数据位相对应的电压被施加之后被激活。 在存储器件的数据读取方法中，读出放大器被激活，然后选择对应于位线的列门。

公开(公告)号：US20100293323A1

公开(公告)日：2010-11-18

申请号：US12843135

申请日：2010-07-26

申请人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

IPC分类号： G06F12/02

CPC分类号： G11C16/26 ,  G11C16/349

摘要： A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

摘要翻译： 公开了闪存设备和闪存系统。 闪速存储装置包括：第一非易失性存储器，包括多个页数据单元，存储页数据;以及当从外部部分施加读命令时，读出并输出存储的页数据; 以及第二非易失性存储器，其包括分别与所述多个页数据单元相邻的多个备用数据单元，存储备用数据，扫描备用数据并在安装文件系统时临时存储相应的信息，读取并输出所存储的备用 应用读命令时的数据。