公开(公告)号：US20160148905A1

公开(公告)日：2016-05-26

申请号：US14823322

申请日：2015-08-11

申请人： Ki Hun YU ,  Tae Young OH ,  Nam Jong KIM ,  Kwang II PARK ,  Chul Sung PARK

发明人： Ki Hun YU ,  Tae Young OH ,  Nam Jong KIM ,  Kwang II PARK ,  Chul Sung PARK

IPC分类号： H01L25/065 ,  G01N25/72 ,  H01L27/108

CPC分类号： H01L25/0657 ,  H01L23/34 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

摘要： In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor. The semiconductor system further includes a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information.

摘要翻译： 在一个示例实施例中，半导体系统包括被配置为产生第一芯片的第一温度信息的第一芯片，第一温度信息基于使用至少一个第一温度传感器的至少一个温度测量。 半导体系统还包括第二芯片，其包括被配置为基于至少第一温度信息来控制的第二温度传感器。

公开(公告)号：US07548485B2

公开(公告)日：2009-06-16

申请号：US11845191

申请日：2007-08-27

申请人： Young-Seung Kim ,  Chul-Sung Park

发明人： Young-Seung Kim ,  Chul-Sung Park

IPC分类号： G11C8/02

CPC分类号： G11C11/413

摘要： A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell array and to read data from the cell, and a bypass control unit configured to control a late write operation and a bypass operation of the peripheral circuit according to mode conversion of the semiconductor memory device. Accordingly, data coherency can be maintained. In addition, dummy cycle time that may occur during the mode conversion can be prevented by generating a mode conversion signal only in response to toggling of a clock signal.

摘要翻译： 提供能够进行同步/异步操作的半导体存储器件及其数据输入/输出方法。 半导体存储器件包括存储单元阵列，外围电路，被配置为向存储单元阵列中的单元写入数据并从单元读取数据;以及旁路控制单元，被配置为控制延迟写入操作和旁路操作 外围电路根据半导体存储器件的模式转换。 因此，可以保持数据一致性。 此外，可以通过仅响应于时钟信号的切换而产生模式转换信号来防止在模式转换期间可能发生的伪周期时间。

公开(公告)号：US20090045844A1

公开(公告)日：2009-02-19

申请号：US12191531

申请日：2008-08-14

申请人： Yong-Hwan NOH ,  Chul-Sung PARK

发明人： Yong-Hwan NOH ,  Chul-Sung PARK

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

摘要翻译： 提供了一种电平转换器和具有使用其的片外驱动器（OCD）的半导体器件。 电平移位器包括多个串联连接的逻辑门，其接收具有第一电源电压电平的第一状态输入信号，并产生具有第二电源电压电平的电平移位的第一状态输出信号。 逻辑门作为电源电压接收至少一个中间电源电压，其具有在第一电源电压电平和第二电源电压电平之间的中间的至少一个电压电平，并且施加到本逻辑门的中间电源电压为 等于或高于施加到先前逻辑门的中间电源电压。

公开(公告)号：US06958947B2

公开(公告)日：2005-10-25

申请号：US10359075

申请日：2003-02-06

申请人： Chul-Sung Park ,  Hyang-Ja Yang ,  Seung-Min Lee ,  Yong-Hwan Noh

发明人： Chul-Sung Park ,  Hyang-Ja Yang ,  Seung-Min Lee ,  Yong-Hwan Noh

IPC分类号： G11C5/14 ,  G11C29/12 ,  G11C29/50

CPC分类号： G11C29/12005 ,  G11C5/147 ,  G11C11/41 ,  G11C29/12 ,  G11C29/50 ,  G11C2207/2254

摘要： A semiconductor memory device which includes an internal voltage generator circuit for adjusting an external power supply voltage and generating first and second internal power supply voltages. The first internal power supply voltage is supplied to a memory cell array via a first power supply line, and the second internal power supply voltage is supplied to a peripheral circuit via a second power supply line. A control circuit controls the internal voltage generator circuit so that the levels of the first and second internal power supply voltages vary depending on a mode of operation.

摘要翻译： 一种半导体存储器件，包括用于调节外部电源电压并产生第一和第二内部电源电压的内部电压发生器电路。 第一内部电源电压经由第一电源线提供给存储单元阵列，并且第二内部电源电压经由第二电源线提供给外围电路。 控制电路控制内部电压发生器电路，使得第一和第二内部电源电压的电平根据操作模式而变化。

公开(公告)号：US5835400A

公开(公告)日：1998-11-10

申请号：US947607

申请日：1997-10-09

申请人： Byung-gil Jeon ,  Chul-sung Park

发明人： Byung-gil Jeon ,  Chul-sung Park

IPC分类号： G11C14/00 ,  G11C7/00 ,  G11C11/22

CPC分类号： G11C11/22

摘要： Ferroelectric memory devices contain an array of ferroelectric memory cells therein and control circuits for enabling the performance of nondestructive read operations. The memory cells of a device contain a ferroelectric memory cell and each memory cell contains a ferroelectric capacitor having a first electrode electrically coupled to a plate line and an access transistor electrically coupled in series between a bit line and a second electrode of the ferroelectric capacitor. A decoder circuit is also provided. The decoder circuit is electrically coupled to the access transistor of the memory cell by a word line and performs the function of, among other things, turning on the access transistor during a read time interval. According to a preferred aspect of the present invention, a pulse generator circuit is provided for initiating nondestructive reading of a quiescent polarization state of the ferroelectric capacitor by applying a single read pulse to the plate line to sweep a polarization state of the ferroelectric capacitor along a noncoercive portion of its hysteresis curve, during the read time interval. A sense amplifier circuit is also provided. The sense amplifier circuit also has a first input electrically coupled to the bit line and a second input electrically coupled to a reference signal line. The sense amplifier performs the function of driving the bit line to a first potential which represents the quiescent polarization state of the ferroelectric capacitor, preferably before termination of the single read pulse.

摘要翻译： 铁电存储器件包含其中的铁电存储器单元阵列和用于实现非破坏性读取操作的控制电路。 器件的存储单元包含铁电存储单元，并且每个存储单元包含铁电电容器，该铁电电容器具有电耦合到板线的第一电极和电阻耦合在铁电电容器的位线和第二电极之间的存取晶体管。 还提供一个解码器电路。 解码器电路通过字线电耦合到存储单元的存取晶体管，并且执行在读取时间间隔期间接通存取晶体管的功能。 根据本发明的优选方面，提供了一种脉冲发生器电路，用于通过向板线施加单个读取脉冲来对铁电电容器的静态极化状态进行非破坏性读取，以扫描强电介质电容器的极化状态沿着 在读取时间间隔期间其滞后曲线的非矫正部分。 还提供读出放大器电路。 感测放大器电路还具有电耦合到位线的第一输入和电耦合到参考信号线的第二输入。 读出放大器执行将位线驱动到表示铁电电容器的静态极化状态的第一电位的功能，优选在单个读取脉冲结束之前。

公开(公告)号：US5805012A

公开(公告)日：1998-09-08

申请号：US653438

申请日：1996-05-24

申请人： Byung-Gil Jeon ,  Chul-Sung Park

发明人： Byung-Gil Jeon ,  Chul-Sung Park

IPC分类号： G11C11/417 ,  G11C5/14 ,  H01L21/8234 ,  H01L27/06 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/08 ,  H03K17/14

CPC分类号： H03K19/00384

摘要： The speed gap between rise and fall times of a buffer biased by a power supply having a power supply voltage, the speed gap varying in a first manner with respect to the power supply voltage and in a second manner inverse to the first manner with respect to a bias current supplied to the buffer, is controlled by generating the bias current such that the bias current varies inversely with respect to the power supply voltage, thereby compensating for fluctuations in the power supply voltage and maintaining the speed gap within a predetermined range when the power supply voltage is greater than a power supply voltage threshold level. The buffer may include a bias transistor controlling the bias current, with the bias current controlled by regulating the differential voltage applied to a control electrode of the bias transistor with an inverse voltage regulator including a control voltage generator for generating a control voltage varying directly with respect to the power supply voltage when the power supply voltage is less than the power supply voltage threshold level and remaining at a control voltage set point level when the power supply voltage is greater than the power supply voltage threshold level, a current feedback regulator for varying the feedback current directly with respect to the power supply voltage, and an output voltage generator for generating the differential voltage from the feedback current and the control voltage such that when the control voltage is at the control voltage set point level, the differential voltage varies inversely with respect to the feedback current.

摘要翻译： 由具有电源电压的电源偏置的缓冲器的上升和下降时间之间的速度差，相对于电源电压以第一种方式变化的速度间隙，以与第一种方式相反的第二种方式相对于 通过产生偏置电流来控制提供给缓冲器的偏置电流，使得偏置电流相对于电源电压反向变化，从而补偿电源电压的波动并且将速度间隙保持在预定范围内，当 电源电压大于电源电压阈值电平。 缓冲器可以包括控制偏置电流的偏置晶体管，偏置电流通过利用包括用于产生直接变化的控制电压的控制电压发生器的反向电压调节器调节施加到偏置晶体管的控制电极的差分电压来控制， 当电源电压小于电源电压阈值电平并且当电源电压大于电源电压阈值电平时保持在控制电压设定点电平时，提供电源电压;电流反馈调节器，用于改变电源电压 反馈电流直接相对于电源电压，以及输出电压发生器，用于从反馈电流和控制电压产生差分电压，使得当控制电压处于控制电压设定点电平时，差分电压与 尊重反馈电流。

公开(公告)号：US09588840B2

公开(公告)日：2017-03-07

申请号：US14225686

申请日：2014-03-26

申请人： Hoi-ju Chung ,  Chul-sung Park ,  Tae-young Oh ,  Jang-woo Ryu ,  Chan-yong Lee ,  Tae-seong Jang ,  Gong-heum Han

发明人： Hoi-ju Chung ,  Chul-sung Park ,  Tae-young Oh ,  Jang-woo Ryu ,  Chan-yong Lee ,  Tae-seong Jang ,  Gong-heum Han

IPC分类号： G06F11/10 ,  G06F11/32

CPC分类号： G06F11/1048 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076

摘要： A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

摘要翻译： 一种操作存储器件的方法包括：响应于接收到的屏蔽写入命令产生内部读取命令，内部读取命令被生成（i）在与所接收的被屏蔽写入命令相关联的写入延迟期间，（ii）之后 在多个屏蔽写入数据位之间接收第一位掩蔽写入数据，以及（iii）与用与掩蔽写入命令对应的地址信号接收的时钟信号的上升沿或下降沿同步; 响应于所述内部读取命令，读取存储在多个存储器单元中的多个位数据，所述多个存储器单元对应于所述地址信号; 以及响应于内部写入命令，在所述多个存储器单元中存储所述多个掩码写入数据位。

公开(公告)号：US20140317470A1

公开(公告)日：2014-10-23

申请号：US14225686

申请日：2014-03-26

申请人： Hoi-ju CHUNG ,  Chul-sung PARK ,  Tae-young OH ,  Jang-woo RYU ,  Chan-yong LEE ,  Tae-seong JANG ,  Gong-heum HAN

发明人： Hoi-ju CHUNG ,  Chul-sung PARK ,  Tae-young OH ,  Jang-woo RYU ,  Chan-yong LEE ,  Tae-seong JANG ,  Gong-heum HAN

IPC分类号： G06F11/10

CPC分类号： G06F11/1048 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076

摘要： A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

摘要翻译： 一种操作存储器件的方法包括：响应于接收到的屏蔽写入命令产生内部读取命令，内部读取命令被生成（i）在与所接收的被屏蔽写入命令相关联的写入延迟期间，（ii）之后 在多个屏蔽写入数据位之间接收第一位掩蔽写入数据，以及（iii）与用与掩蔽写入命令对应的地址信号接收的时钟信号的上升沿或下降沿同步; 响应于所述内部读取命令，读取存储在多个存储器单元中的多个位数据，所述多个存储器单元对应于所述地址信号; 以及响应于内部写入命令，在所述多个存储器单元中存储所述多个掩码写入数据位。

公开(公告)号：US20100194433A1

公开(公告)日：2010-08-05

申请号：US12759252

申请日：2010-04-13

申请人： Yong-Hwan NOH ,  Chul-Sung PARK

发明人： Yong-Hwan NOH ,  Chul-Sung PARK

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

摘要翻译： 提供了一种电平转换器和具有使用其的片外驱动器（OCD）的半导体器件。 电平移位器包括多个串联连接的逻辑门，其接收具有第一电源电压电平的第一状态输入信号，并产生具有第二电源电压电平的电平移位的第一状态输出信号。 逻辑门作为电源电压接收至少一个中间电源电压，其具有在第一电源电压电平和第二电源电压电平之间的中间的至少一个电压电平，并且施加到本逻辑门的中间电源电压为 等于或高于施加到先前逻辑门的中间电源电压。

公开(公告)号：US07362128B2

公开(公告)日：2008-04-22

申请号：US11153755

申请日：2005-06-14

申请人： Myung-Han Choi ,  Young-Dae Lee ,  Chul-Sung Park

发明人： Myung-Han Choi ,  Young-Dae Lee ,  Chul-Sung Park

IPC分类号： H03K17/16

CPC分类号： H03K19/0005

摘要： A programmable impedance control circuit for use in a semiconductor device having an impedance range shifting function prevents or substantially reduces an impedance detection failure based on an environment change. An impedance detector includes a first array driver, a second array driver, and an impedance matching transistor array and a range shifting transistor array independently controlled by the first and second array drivers. A comparator each compares first and second output voltage levels of the impedance detector with an array reference voltage, and outputs an up/down signal as the comparison result. A counter performs an up/down counting in response to the up/down signal, and outputs control code data. A range shifting circuit monitors a counting output of the counter and so generates range shifting data. Whereby, even if there is an environment change on a manufacturing process, power source voltage or operating temperature, etc., an impedance matching and correction operation can be performed without a waste of impedance matching transistor array and control code.

摘要翻译： 用于具有阻抗范围移位功能的半导体器件中的可编程阻抗控制电路防止或基本上减少了基于环境变化的阻抗检测失败。 阻抗检测器包括第一阵列驱动器，第二阵列驱动器和阻抗匹配晶体管阵列以及由第一和第二阵列驱动器独立控制的量程移位晶体管阵列。 比较器每个将阻抗检测器的第一和第二输出电压电平与阵列参考电压进行比较，并输出上/下信号作为比较结果。 计数器响应于上/下信号执行向上/向下计数，并输出控制代码数据。 范围移动电路监视计数器的计数输出，因此产生范围移位数据。 因此，即使在制造过程中存在环境变化，电源电压或工作温度等，也可以进行阻抗匹配和校正操作，而不会浪费阻抗匹配晶体管阵列和控制代码。