公开(公告)号：US20210303302A1

公开(公告)日：2021-09-30

申请号：US17141082

申请日：2021-01-04

Applicant: NVIDIA Corporation

Inventor： Brent Ralph Boswell ,  Ming Y. Siu ,  Jack H. Choquette ,  Jonah M. Alben ,  Stuart Oberman

IPC: G06F9/30 ,  G06T1/20 ,  G06F9/38

Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.

公开(公告)号：US20190377549A1

公开(公告)日：2019-12-12

申请号：US16001838

申请日：2018-06-06

Applicant: NVIDIA Corporation

Inventor： Jonah M. Alben ,  Paulius Micikevicius ,  Hao Wu ,  Ming Yiu Siu

IPC: G06F7/499

Abstract: A method, computer readable medium, and system are disclosed for rounding numerical values. A set of bits from an input value is identified as a rounding value. A second set of bits representing a second value is extracted from the input value and added with the rounding value to produce a sum. The sum is truncated to produce the rounded output value. Thus, the present invention provides a stochastic rounding technique that rounds up an input value as a function of a second value and a rounding value, both of which were obtained from the input value. When the second value and rounding value are obtained from consistent bit locations of the input value, the resulting output value is deterministic. Stochastic rounding, which is deterministic, is advantageously applicable in deep learning applications.

公开(公告)号：US20190324747A1

公开(公告)日：2019-10-24

申请号：US16459191

申请日：2019-07-01

Applicant: NVIDIA Corporation

Inventor： Brent Ralph Boswell ,  Ming Y. Siu ,  Jack H. Choquette ,  Jonah M. Alben ,  Stuart Oberman

IPC: G06F9/30 ,  G06T1/20 ,  G06F9/38

Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.

公开(公告)号：US10096086B2

公开(公告)日：2018-10-09

申请号：US14846737

申请日：2015-09-05

Applicant: NVIDIA CORPORATION

Inventor： Yury Y. Uralsky ,  Jonah M. Alben ,  Ankan Banerjee ,  Gregory Massal ,  Thomas Petersen ,  Oleg Kuznetsov ,  Eric B. Lum ,  Prakshep Mehta

IPC: G06T5/00 ,  G06T11/00 ,  G06T1/20 ,  G06T5/20

Abstract: A raster unit is configured to generate different sample patterns for adjacent pixels within a given frame. In addition, the raster unit may adjust the sample patterns between frames. The raster unit includes an index unit that selects a sample pattern table for use with a current frame. For a given pixel, the index unit extracts a sample pattern from the selected sample pattern table. The extracted sample pattern is used to generate coverage information for the pixel. The coverage information for all pixels is then used to generate an image. The resultant image may then be filtered to reduce or remove artifacts induced by the changing of sample locations.

公开(公告)号：US09170980B2

公开(公告)日：2015-10-27

申请号：US13973952

申请日：2013-08-22

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  Thomas Hastings Greer, III

IPC: G11C11/40 ,  G06F15/78

CPC classification number: G06F15/7864 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括处理器芯片，系统功能芯片和被配置为包括处理器芯片，系统功能芯片和互连电路的MCM封装。 处理器芯片被配置为包括第一接地参考的单端信令接口电路。 在MCM封装内制造的第一组电迹线，用于将第一单端信令接口电路耦合到互连电路。 系统功能芯片被配置为包括第二单端信令接口电路和主机接口。 MCM封装中制造的第二组电迹线，用于将主机接口耦合到MCM封装的至少一个外部引脚。 在一个实施例中，每个单端信令接口有利地实现接地参考的单端信令。

公开(公告)号：US08786345B2

公开(公告)日：2014-07-22

申请号：US13852987

申请日：2013-03-28

Applicant: NVIDIA Corporation

Inventor： Jonah M. Alben ,  William J. Dally

IPC: H03K3/00

CPC classification number: H03K3/286 ,  H03K3/012 ,  H03K3/356139 ,  H03K3/356191

Abstract: One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations, The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant, The output signal Q is set or reset at the rising clock edge using a single- trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract translation: 本发明的一个实施例提出了一种使用完全静态且对制造工艺变化不敏感的单触发低能触发器电路来捕获和存储输入信号电平的技术。单触发低电平触发器电路 能量触发器电路仅向时钟信号提供三个晶体管栅极负载，并且当输入信号保持恒定时，内部节点都不会切换。使用单触发子电路在上升时钟沿设置或复位输出信号Q 。 时钟信号为低电平时，可以设置置位或复位，并在时钟的上升沿触发置位或复位。

公开(公告)号：US20130214839A1

公开(公告)日：2013-08-22

申请号：US13852987

申请日：2013-03-28

Applicant: NVIDIA Corporation

Inventor： Jonah M. Alben ,  William J. Dally

IPC: H03K3/286

CPC classification number: H03K3/286 ,  H03K3/012 ,  H03K3/356139 ,  H03K3/356191

Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. The output signal Q is set or reset at the rising clock edge using a single-trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract translation: 本发明的一个实施例提出了一种技术，用于使用完全静态且对制造工艺变化不敏感的单触发低能触发器电路来捕获和存储输入信号电平的技术。 单触发低能触发器电路仅对时钟信号提供三个晶体管栅极负载，并且当输入信号保持不变时，内部节点都不会切换。 输出信号Q在上升时钟沿使用单触发子电路设置或复位。 时钟信号为低电平时，可以设置置位或复位，并在时钟的上升沿触发置位或复位。