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67 条记录 (耗时 0.036 秒)

    Inverter based return-to-zero (RZ)+ Non-RZ (NRZ) signaling
    31.
    发明申请
    Inverter based return-to-zero (RZ)+ Non-RZ (NRZ) signaling 有权
    基于逆变器的归零（RZ）+非RZ（NRZ）信号

    公开(公告)号：US20080152356A1

    公开(公告)日：2008-06-26

    申请号：US11644348

    申请日：2006-12-22

    申请人： Dinesh Somasekhar ,  Sourav Saha ,  Gregory E. Ruhl ,  Ashoke Ravi

    发明人： Dinesh Somasekhar ,  Sourav Saha ,  Gregory E. Ruhl ,  Ashoke Ravi

    IPC分类号： H04B10/04

    CPC分类号： H04B10/5162

    摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for inverter based return-to-zero (RZ)+non-RZ (NRZ) signaling. The interface circuit contains multiple ganged drivers (some or all of them are turned on at one point of time) and edge detection circuitry (to configure/modulate edges of the input data signal). These two circuits together generate weighted return-to-zero (RZ)+non-RZ (NRZ) signal.

    摘要翻译： 本发明的实施例一般涉及用于基于逆归零（RZ）+非RZ（NRZ）信令的基于逆变器的系统，方法和装置。 接口电路包含多个组合的驱动器（其中一些或全部在一个时间点打开）和边沿检测电路（以配置/调制输入数据信号的边沿）。 这两个电路一起产生加权归零（RZ）+非RZ（NRZ）信号。

    Adaptively extending tunable range of frequency in a closed loop
    32.
    发明授权
    Adaptively extending tunable range of frequency in a closed loop 有权
    在闭环中自适应地扩展频率的可调范围

    公开(公告)号：US07119628B2

    公开(公告)日：2006-10-10

    申请号：US10985511

    申请日：2004-11-10

    申请人： Ashoke Ravi ,  Krishnamurthy Soumyanath

    发明人： Ashoke Ravi ,  Krishnamurthy Soumyanath

    IPC分类号： H03L7/08

    CPC分类号： H03L7/18 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/107

    摘要： A semiconductor device or a circuit includes a controllable oscillator and circuitry that senses a voltage which may control the controllable oscillator and digitally controls a gain compensation, adaptively compensating for a drop in a gain against overall loop gain within a closed loop. In one embodiment, a single supply source may be used to power the closed loop while a variable gain stage that is digitally controllable may adjust the gain in a feed-forward manner based on the drop.

    摘要翻译： 半导体器件或电路包括可控振荡器和电路，其感测可控制可控振荡器并且数字控制增益补偿的电压，自适应地补偿增益中的下降与闭环内的整体环路增益。 在一个实施例中，可以使用单个供电源为闭环供电，而可数字控制的可变增益级可以基于该下降以前馈方式调节增益。

    DIGITAL PHASED ARRAY
    34.
    发明公开
    DIGITAL PHASED ARRAY 审中-公开

    公开(公告)号：US20230283311A1

    公开(公告)日：2023-09-07

    申请号：US17561399

    申请日：2021-12-23

    申请人： Benjamin Jann ,  Ashoke Ravi ,  Paolo Madoglio

    发明人： Benjamin Jann ,  Ashoke Ravi ,  Paolo Madoglio

    IPC分类号： H04B1/16 ,  H04B7/06 ,  H04B7/17 ,  H04B1/04

    CPC分类号： H04B1/1607 ,  H04B1/04 ,  H04B7/0602 ,  H04B7/17 ,  H04B2001/0408

    摘要： A wireless communication device includes an antenna array with multiple antenna elements, an array of power amplifiers, and an array of phase shifters. Each antenna element is coupled to a power amplifier and a phase shifter. The device also includes transmitter circuitry coupled to the antenna array to encode a constant amplitude signal, which includes a power amplifier enable code to indicate which power amplifiers are to run in a subsequent data sample and a beam direction code to control beam direction of each phase shifter of the array of phase shifters in the subsequent data sample. The constant amplitude signal is then provided to the array of antenna elements and amplitude and phase modulation is combined over an air interface into a composite modulated signal.

    Input jitter attenuation in a phase-locked loop
    39.
    发明授权
    Input jitter attenuation in a phase-locked loop 有权
    在锁相环中输入抖动衰减

    公开(公告)号：US06703878B2

    公开(公告)日：2004-03-09

    申请号：US10206778

    申请日：2002-07-25

    申请人： Krishnamurhty Soumyanath ,  Ashoke Ravi

    发明人： Krishnamurhty Soumyanath ,  Ashoke Ravi

    IPC分类号： H03L700

    CPC分类号： H03L7/18 ,  H03L7/093 ,  H03L7/1978

    摘要： To attenuate the effects of phase noise and input jitter introduced in the reference frequency of the PLL, the zeros of the forward path transfer function are removed. As a result, the forward path does not amplify any phase noise or input jitter appearing in the reference frequency. However, overall loop stability is maintained by placing the zeros in the feedback path of the PLL. A discriminator may be placed in the feedback path to introduce the zero in the loop gain transfer function and provide stability.

    摘要翻译： 为了衰减在PLL的参考频率中引入的相位噪声和输入抖动的影响，前向路径传递函数的零被去除。 因此，正向通路不会放大出现在参考频率中的任何相位噪声或输入抖动。 然而，通过将零置于PLL的反馈路径中来保持总体环路稳定性。 可以在反馈路径中放置鉴别器以将零引入环路增益传递函数并提供稳定性。

    Transformer coupled quadrature tuned oscillator
    40.
    发明授权
    Transformer coupled quadrature tuned oscillator 失效
    变压器耦合正交调谐振荡器

    公开(公告)号：US06639481B1

    公开(公告)日：2003-10-28

    申请号：US10224684

    申请日：2002-08-20

    申请人： Ashoke Ravi ,  Krishnamurthy Soumyanath

    发明人： Ashoke Ravi ,  Krishnamurthy Soumyanath

    IPC分类号： H03L700

    CPC分类号： H03L7/00

    摘要： First and second oscillator cells include tank circuits that may be tuned to a desired resonant frequency using varactors as variable reactance devices in a phase-shifting network. First and second transformers are connected to the oscillator cells to control the varactors.

    摘要翻译： 第一和第二振荡器单元包括可以使用变容二极管作为相移网络中的可变电抗装置来调谐到期望谐振频率的振荡电路。 第一和第二变压器连接到振荡器单元以控制变容二极管。