公开(公告)号：US08018290B2

公开(公告)日：2011-09-13

申请号：US12439764

申请日：2007-10-15

Applicant: Hiroyuki Mizutani ,  Kazuhiro Nishida ,  Masaomi Tsuru ,  Kenji Kawakami ,  Morishige Hieda ,  Moriyasu Miyazaki

Inventor： Hiroyuki Mizutani ,  Kazuhiro Nishida ,  Masaomi Tsuru ,  Kenji Kawakami ,  Morishige Hieda ,  Moriyasu Miyazaki

IPC: H03B25/00

CPC classification number: H03B5/1847 ,  G01S7/35

Abstract: An output terminal 6 is provided at the connecting point 5 between the collector terminal of a transistor 1 and an open-ended stub 4 by connecting the open-ended stub 4 to the collector terminal of the transistor 1, the open-ended stub 4 having a line length equal to a quarter of the wavelength of a signal of frequency 2N·F0 or 2N times the oscillation frequency F0. In addition, an output terminal 9 is provided at a connecting point 8 located at a distance equal to a quarter of the wavelength of a signal of oscillation frequency F0 from the end of an open-ended stub 7 by connecting the open-ended stub 7 to the base terminal of the transistor 1, the open-ended stub 7 having a line length longer than a quarter of the wavelength of the signal of oscillation frequency F0.

Abstract translation: 通过将开路端子4连接到晶体管1的集电极端子，在晶体管1的集电极端子与开路短截线端子4之间的连接点5处设置有输出端子6，开路短路端子4具有 线长度等于频率为2N·F0或振荡频率F0的2N倍的信号波长的四分之一。 此外，输出端子9设置在连接点8处，该连接点8通过连接开放端短截线7而设置在距离开放端短截线7的端部等于振荡频率F0的信号的波长的四分之一的距离处 到晶体管1的基极，具有比振荡频率F0的信号的波长的四分之一长的线路长度的开路短截线7。

公开(公告)号：US20090115546A1

公开(公告)日：2009-05-07

申请号：US11571577

申请日：2005-07-01

Applicant: Anthony KERSELAERS ,  Felix ELSEN

Inventor： Anthony KERSELAERS ,  Felix ELSEN

IPC: H03C3/09 ,  H03B25/00

CPC classification number: H03C3/22 ,  H03B5/1203 ,  H03B5/1231 ,  H03B5/1243 ,  H03B25/00 ,  H03B2200/007 ,  H03C3/09

Abstract: Oscillators (10) which oscillate at a fundamental frequency also generate harmonics. The fundamental frequency or a lower harmonic is used for feedback purposes, and a harmonic higher than either the fundamental frequency or the lower harmonic is used for output purposes. As a result, the oscillators (10) operate at a lower frequency than an output frequency and are low cost. Synthesizers (20) coupled to the oscillators (10) also operate at this lower frequency, and modulators (5) comprising such oscillators (10) and synthesizers (20) are low cost. A lower power consumption and less sensitivity to disturbing fields are further advantages. Filtering has become less complicated, and a smaller number of components has resulted in smaller dimensions. The oscillators (10) comprise tuning circuits (11) and amplifiers (12), which amplifiers (12) are fed back via feedback circuits (13). Such an amplifier (12) may comprise just a single transistor (40).

Abstract translation: 以基频振荡的振荡器（10）也产生谐波。 基频或低次谐波用于反馈目的，并且高于基波或低次谐波的谐波用于输出目的。 结果，振荡器（10）的工作频率比输出频率低，成本低。 耦合到振荡器（10）的合成器（20）也以较低的频率工作，并且包括这种振荡器（10）和合成器（20）的调制器（5）是低成本的。 较低的功耗和对干扰场的敏感性较低是进一步的优点。 过滤变得不那么复杂，并且更少的部件已经导致更小的尺寸。 振荡器（10）包括调谐电路（11）和放大器（12），放大器（12）经反馈电路（13）反馈。 这种放大器（12）可以仅包括单个晶体管（40）。

公开(公告)号：US20050174183A1

公开(公告)日：2005-08-11

申请号：US11099517

申请日：2005-04-06

Applicant: Suguru Tachibana ,  Tomonari Morishita ,  Fukuji Kihara ,  Makoto Kubota

Inventor： Suguru Tachibana ,  Tomonari Morishita ,  Fukuji Kihara ,  Makoto Kubota

IPC: H03B5/36 ,  H03B25/00

CPC classification number: H03B5/364

Abstract: A crystal oscillation circuit has a reduced circuit area and enables to stably oscillate at low consumed current. The crystal oscillation circuit includes an oscillating amplifier and a constant voltage generator. The oscillating amplifier excites a resonator composed of a resistor, a crystal oscillator and a capacitor. The constant voltage generator includes a one-stage differential circuit composed of a transistor and a capacitor for suppressing transient fluctuation of a constant voltage Vreg for generating the constant voltage Vreg served as a supply voltage for the oscillating amplifier. By generating the constant voltage Vreg through the one-stage differential circuit, the phase lag of the constant voltage Vreg reaches 90 degrees at most. This eliminates the necessity of a phase compensation capacitor, resulting in making the circuit area smaller and realizing the stable oscillation at low consumed current.

Abstract translation: 晶体振荡电路具有减小的电路面积，能够在低消耗电流下稳定地振荡。 晶体振荡电路包括振荡放大器和恒压发生器。 振荡放大器激发由电阻器，晶体振荡器和电容器组成的谐振器。 恒定电压发生器包括由晶体管和电容器组成的一级差分电路，用于抑制用作产生用于振荡放大器的电源电压的恒定电压Vreg的恒定电压Vreg的瞬变波动。 通过产生通过一级差分电路的恒定电压Vreg，恒定电压Vreg的相位滞后最多达到90度。 这消除了相位补偿电容器的必要性，导致电路面积更小并且在低消耗电流下实现稳定的振荡。

公开(公告)号：US20050122177A1

公开(公告)日：2005-06-09

申请号：US10999712

申请日：2004-11-30

Applicant: Yasuhiro Ikarashi

Inventor： Yasuhiro Ikarashi

IPC: H03K5/00 ,  H03B5/02 ,  H03B25/00 ,  H03L7/099 ,  H03B1/00

CPC classification number: H03B5/02 ,  H03B25/00 ,  H03B2200/0034 ,  H03B2200/007

Abstract: The voltage controlled oscillator includes an oscillating transistor, and first and second inductance elements which are connected in series and provided between an output terminal of the oscillating transistor and a high frequency ground point Vcc. Oscillating signals are output from the output terminal of the oscillating transistor and a connecting point between the first inductance element and the second inductance element, respectively. The output terminal of the oscillating transistor outputs a fundamental wave having a high level, and the connecting point between two inductance elements outputs the harmonic wave, suppressing the fundamental wave.

Abstract translation: 压控振荡器包括振荡晶体管和串联连接并设置在振荡晶体管的输出端子与高频接地点Vcc之间的第一和第二电感元件。 振荡信号从振荡晶体管的输出端子和第一电感元件与第二电感元件之间的连接点分别输出。 振荡晶体管的输出端子输出高电平的基波，两个电感元件之间的连接点输出谐波，抑制基波。

公开(公告)号：US06850122B2

公开(公告)日：2005-02-01

申请号：US10401024

申请日：2003-03-28

Applicant: Ashoke Ravi ,  Krishnamurthy Soumyanath

Inventor： Ashoke Ravi ,  Krishnamurthy Soumyanath

IPC: H03B5/12 ,  H03B27/00 ,  H03K3/354 ,  H03B25/00

CPC classification number: H03B27/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03K3/354

Abstract: A quadrature oscillator includes a master tuned oscillator and two injection-locked slave tuned oscillators.

Abstract translation: 正交振荡器包括主调谐振荡器和两个注入锁定从动调谐振荡器。

公开(公告)号：US5668504A

公开(公告)日：1997-09-16

申请号：US678486

申请日：1996-07-09

Applicant: Rui Paulo Rodriques Ramalho

Inventor： Rui Paulo Rodriques Ramalho

IPC: H04N7/26 ,  H03B25/00 ,  H03B27/00 ,  H03L7/081 ,  H03L7/099 ,  H03L7/16 ,  H03L7/183 ,  H03L7/197 ,  H03L7/06 ,  H03K5/00

CPC classification number: H03L7/16 ,  H03L7/081 ,  H03L7/0995 ,  H03L7/183 ,  H03B25/00 ,  H03B27/00 ,  H03L7/1976

Abstract: A frequency synthesizer including a phase-locked loop, an oscillator of which supplies n phases with increasing delays of a fast clock signal synchronized on a reference frequency, each of said n phases being sent onto a same number m of fractional dividers having their respective outputs sent onto m jitter compensators which each issue, based on said n phases, a clock signal synchronized on said reference frequency.

Abstract translation: 一种频率合成器，包括锁相环，其振荡器为在参考频率上同步的快速时钟信号的增加的延迟提供n个相位，所述n个相位中的每一个被发送到具有它们各自的输出的相同数量的分数分频器 发送到m个抖动补偿器，每个抖动补偿器基于所述n个相位发出在所述参考频率上同步的时钟信号。

公开(公告)号：US5263197A

公开(公告)日：1993-11-16

申请号：US762759

申请日：1991-09-20

Applicant: Yoshiharu Manjo ,  Charles R. McMurray ,  Tadashi Ohga

Inventor： Yoshiharu Manjo ,  Charles R. McMurray ,  Tadashi Ohga

IPC: H03B1/00 ,  H03B5/36 ,  H03B19/14 ,  H03B25/00 ,  H03D7/16 ,  H03J5/02 ,  H04B1/28 ,  H04B1/30 ,  H04B1/26

CPC classification number: H03J5/0272 ,  H03B25/00 ,  H04B1/28 ,  H04B1/30 ,  H03B19/14 ,  H03B2201/011 ,  H03B2201/0208 ,  H03B5/362 ,  H03D7/16

Abstract: A two-stage direct conversion receiver. A first mixer (13) converts the incoming signal to an intermediate frequency (IF) signal. A second mixer (16) converts the IF signal to a baseband signal. A detector (17), receiver logic circuit (18), and alerting device circuit (19) act upon the baseband output signal. A two port oscillator (14) provides a fundamental frequency output (FO) and a tripled output frequency (3 FO). The tripled output frequency is again tripled (9 FO) by a frequency multiplier (15) and is provided as a mixing signal to the first mixer (13). The fundamental frequency output is provided to a phase locked loop (20, 21, 22). The output frequency (FV) of the phase locked loop is doubled (2 FV) by a frequency multiplier (23) and provided to a phase shift circuit (24). The output of the phase shift circuit (24) is provided as the second mixing signal to the second mixer (16). The phase locked loop comprises a phase locked loop controller (20), a phase locked loop filter (21), and a voltage controlled oscillator (22). The main oscillator (14) is configured as a crystal controlled Colpitts oscillator, which has an emitter resonant circuit selected to produce oscillation at the fundamental frequency, and a collector resonant circuit selected to extract the third harmonic of the fundamental oscillation frequency. A single active device can therefore provide both the fundamental frequency and the third harmonic frequency. Calibration of the receiver is effected by simply tuning the oscillator (14) to produce a baseband output signal at the output of the second mixer (16). Single step calibration is therefore effected because the voltage controlled oscillator (22) is locked to the main oscillator (14).

Abstract translation: 两级直接转换接收机。 第一混频器（13）将输入信号转换成中频（IF）信号。 第二混频器（16）将IF信号转换为基带信号。 检测器（17），接收器逻辑电路（18）和报警装置电路（19）作用于基带输出信号。 双端口振荡器（14）提供基频输出（FO）和三倍输出频率（3 FO）。 倍增输出频率由倍频器（15）再三倍（9F），并作为混合信号提供给第一混频器（13）。 基频输出被提供给锁相环（20,21,22）。 锁相环的输出频率（FV）由倍频器（23）加倍（2 FV），并提供给相移电路（24）。 将相移电路（24）的输出作为第二混频信号提供给第二混频器（16）。 锁相环包括锁相环控制器（20），锁相环滤波器（21）和压控振荡器（22）。 主振荡器（14）被配置为晶体控制的Colpitts振荡器，其具有选择用于产生基频振荡的发射极谐振电路和选择为提取基波振荡频率的三次谐波的集电极谐振电路。 因此，单个有源器件可以提供基频和三次谐波频率。 通过简单地调谐振荡器（14）来在第二混频器（16）的输出处产生基带输出信号来实现接收机的校准。 因此，单步校准是因为压控振荡器（22）被锁定到主振荡器（14）。

公开(公告)号：US4462114A

公开(公告)日：1984-07-24

申请号：US431425

申请日：1982-09-30

Applicant: Norman W. Parker

Inventor： Norman W. Parker

IPC: H03C3/00 ,  H04B1/68 ,  H04B14/00 ,  H03B25/00 ,  H04B1/62

CPC classification number: H03C3/005 ,  H04B1/68 ,  H04B14/006

Abstract: A single carrier is amplitude-modulated by a signal which is a transform (as the sine function) of the audio signal, and one set of sidebands is removed. In a receiver, the signal can be recovered by first deriving the Hilbert transform of the sine transform, and multiplying it by the signum of the derivative of the original audio signal to obtain the cosine transform. The sine and cosine transforms are then decoded to obtain the original audio signal. A circuit for deriving the signum of the derivative of a signal is disclosed.

Abstract translation: 单个载波由作为音频信号的变换（作为正弦函数）的信号进行幅度调制，并且去除一组边带。 在接收机中，可以通过首先导出正弦变换的希尔伯特变换，并将其乘以原始音频信号的导数的符号来获得余弦变换来恢复信号。 然后对正弦和余弦变换进行解码以获得原始音频信号。 公开了一种用于导出信号导数的符号的电路。

公开(公告)号：US4052673A

公开(公告)日：1977-10-04

申请号：US718802

申请日：1976-08-30

Applicant: Gerald Bernard Herzog

Inventor： Gerald Bernard Herzog

IPC: H03L7/18 ,  H03B19/00 ,  H03B19/14 ,  H03K7/06 ,  H03L7/099 ,  H03L7/183 ,  H04N5/50 ,  H04B1/04 ,  H03B19/10 ,  H03B25/00 ,  H04B1/28

CPC classification number: H03L7/183 ,  H03K7/06 ,  H03L7/0995 ,  H04N5/50

Abstract: A voltage controlled oscillator which, for example, may be utilized in a phase locked loop, includes an odd number (n) of cascaded COS-MOS inverter stages with a feedback path coupling the output of the last stage to the input of the first stage to form a ring configuration. The ring configuration oscillates at a frequency f.sub.1 determined by the transconductances of the inverter stages and the shunt capacitances between the stages. Signals comprising impulses of current having frequency components at f.sub.1 and 2f.sub.1 flow through the power supply inputs of each of the stages as they successively are switched from one state to another. A frequency selective impedance path is coupled between a source of power supply voltage and the power supply inputs of each of the stages to develop a second signal having a frequency f.sub.2 equal to a multiple nf.sub.1 or 2nf.sub.1. The voltage applied to the commonly connected power supply inputs may be controlled to control f.sub.1 and, consequently, f.sub.2.

公开(公告)号：US3956703A

公开(公告)日：1976-05-11

申请号：US565851

申请日：1975-04-07

Applicant: Johannes Noordanus ,  Marie Marcel Arnold Antoine Ghislain Verstraelen

Inventor： Johannes Noordanus ,  Marie Marcel Arnold Antoine Ghislain Verstraelen

IPC: H03L7/18 ,  H03B19/00 ,  H03B25/00 ,  H03K5/00 ,  H03L7/22 ,  H03L7/23

CPC classification number: H03L7/23

Abstract: Multichannel generator for at will generating any one of a plurality of channel frequencies in the GHz band which are spaced from one another by equal channel distances. The multichannel generator is constituted by a frequency synthesis device which comprises two phase-locked loops which each comprise an oscillator, a divider adjustable in discrete steps and a phase detector to which a reference frequency is applied. The adjustable dividers keep in step. One of the oscillators is coupled via a fixed divider and a mixer stage to the adjustable frequency divider included in the relevant loop. The signal injected into the mixer stage is derived from the other oscillator. The influence of the fixed divider on the value of the channel spacing is avoided by a particular relationship between the reference frequencies supplied to the phase detectors.

Abstract translation: 用于at的多通道发生器将产生在GHz频带中通过相等的信道距离彼此间隔开的多个信道频率中的任何一个。 多通道发生器由频率合成装置构成，频率合成装置包括两个锁相环，每个锁相环包括一个振荡器，一个分立可调的分频器和一个施加了参考频率的相位检测器。 可调分频器保持步进。 其中一个振荡器通过固定分频器和混频器级耦合到相关回路中包括的可调分频器。 注入混合器级的信号来自另一个振荡器。 通过提供给相位检测器的参考频率之间的特定关系来避免固定分频器对通道间隔的影响。