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31.发明授权Method of improving gate activation by employing atomic oxygen enhanced oxidation 失效通过采用原子氧增强氧化改善浇口活化的方法公开(公告)号：US06566210B2
公开(公告)日：2003-05-20
申请号：US09905233
申请日：2001-07-13
IPC分类号： H01L21336
CPC分类号： H01L21/28035 , H01L21/32105 , H01L29/4916
摘要： The present invention provides a method of preparing a Si-based metal-insulator-semiconductor (MIS) transistor which prevents the polycrystalline grains of the gate conductor from getting significantly larger by reducing the thermal budget of the sidewall oxidation process. The thermal budget of the inventive sidewall oxidation process is reduced one or two orders of magnitude over conventional prior art sidewall oxidation processes by utilizing atomic oxygen as the oxidizing ambient. The present invention also provides Si-based MIS transistors having a gate conductor having grain sizes of about 0.1, preferably 0.05, &mgr;m or less.
摘要翻译： 本发明提供一种制备Si基金属 - 绝缘体半导体（MIS）晶体管的方法，其通过降低侧壁氧化工艺的热量预算来防止栅极导体的多晶晶粒变得明显更大。 通过利用原子氧作为氧化环境，本发明的侧壁氧化过程的热预算比常规现有技术的侧壁氧化过程减少一到两个数量级。 本发明还提供具有晶体尺寸为约0.1μm，优选0.05μm或更小的栅极导体的Si基MIS晶体管。
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32.发明授权Method for forming high performance CMOS devices with elevated sidewall spacers 有权用于形成具有升高的侧壁间隔物的高性能CMOS器件的方法公开(公告)号：US06509221B1
公开(公告)日：2003-01-21
申请号：US10000695
申请日：2001-11-15
IPC分类号： H01L218238
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/823864 , H01L29/7833
摘要： A method is described for making elevated sidewall spacers on the gate structure of a semiconductor device. A first insulating layer is deposited on the substrate, so that an upper portion of each of the sidewalls extends above the layer. A second insulating layer is deposited on the first layer and on the gate structure. Portions of the second layer disposed on the first layer and on the top surface of the gate structure are removed, so that a remaining portion of the second layer is disposed on the upper portion of each of the sidewalls. The first layer is then removed, so that the remaining portion of the second layer on each of the sidewalls projects laterally therefrom and is elevated with respect to the substrate. This structure is used to implant PFET and NFET extension regions without dose loss.
摘要翻译： 描述了一种用于在半导体器件的栅极结构上制造升高的侧壁间隔物的方法。 第一绝缘层沉积在衬底上，使得每个侧壁的上部在层上延伸。 第二绝缘层沉积在第一层和栅极结构上。 去除设置在栅极结构的第一层和顶表面上的第二层的部分，使得第二层的剩余部分设置在每个侧壁的上部。 然后去除第一层，使得每个侧壁上的第二层的剩余部分从其侧向突出并且相对于衬底升高。 该结构用于注入PFET和NFET延伸区而没有剂量损失。
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公开(公告)号：US07923782B2
公开(公告)日：2011-04-12
申请号：US10708378
申请日：2004-02-27
申请人： Huilong Zhu , Philip J. Oldiges , Bruce B. Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip J. Oldiges , Bruce B. Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。
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公开(公告)号：US07388257B2
公开(公告)日：2008-06-17
申请号：US10711200
申请日：2004-09-01
申请人： Bruce B. Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
发明人： Bruce B. Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
IPC分类号： H01L27/01
CPC分类号： H01L29/785 , H01L29/66795
摘要： A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.
摘要翻译： 多栅极器件具有用于栅极顶部沟道的高k电介质层和用于finFET器件的保护层。 高k电介质层被放置在finFET的沟道的顶表面上，并且可以减少或消除沟道中的硅消耗。 在顶表面上使用高k电介质层减少了与高k电介质相关的滞后和迁移率降低。 保护层可以在蚀刻过程中保护高k电介质层。
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公开(公告)号：US07312134B2
公开(公告)日：2007-12-25
申请号：US11741441
申请日：2007-04-27
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7843 , Y10S438/938
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.
摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。
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36.发明授权Oxidation method for altering a film structure and CMOS transistor structure formed therewith 失效用于改变由其形成的膜结构和CMOS晶体管结构的氧化方法公开(公告)号：US06982196B2
公开(公告)日：2006-01-03
申请号：US10605889
申请日：2003-11-04
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203
摘要： A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.
摘要翻译： 提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。 在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。 还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。 然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率 另一个是NFET和PFET。
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37.发明授权Method for forming a multi-gate device with high k dielectric for channel top surface 失效用于形成用于沟道顶表面的具有高k电介质的多栅极器件的方法公开(公告)号：US07785943B2
公开(公告)日：2010-08-31
申请号：US11928787
申请日：2007-10-30
申请人： Bruce B. Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
发明人： Bruce B. Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L29/66795
摘要： Method for providing a transistor that includes the steps of providing a silicon on insulator layer, providing a silicon oxide insulation layer, providing a dielectric layer, removing at least a portion of the silicon oxide insulation layer and the dielectric layer to form a gate stack, and forming a gate electrode. The gate electrode covers a portion of the gate stack.
摘要翻译： 一种用于提供晶体管的方法，包括以下步骤：提供绝缘体上硅层，提供氧化硅绝缘层，提供电介质层，去除氧化硅绝缘层和电介质层的至少一部分以形成栅叠层; 并形成栅电极。 栅电极覆盖栅叠层的一部分。
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公开(公告)号：US07741166B2
公开(公告)日：2010-06-22
申请号：US11318818
申请日：2005-12-27
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203
摘要： A method is provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A method is further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.
摘要翻译： 提供了一种方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。 在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。 还提供了一种方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。 然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率 另一个是NFET和PFET。
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39.发明申请SEMICONDUCTOR DEVICE STRUCTURE WITH ACTIVE REGIONS HAVING DIFFERENT SURFACE DIRECTIONS 审中-公开具有不同表面方向的主动区域的半导体器件结构公开(公告)号：US20080142852A1
公开(公告)日：2008-06-19
申请号：US12032913
申请日：2008-02-18
IPC分类号： H01L27/092
CPC分类号： H01L29/045 , H01L21/76275 , H01L21/76278 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/7842
摘要： Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.
摘要翻译： 公开了同时实现nFET和pFET器件以及朝向一个方向的栅极的最佳应力类型和电流流动的半导体结构和方法。 该方法的一个实施例包括将具有第一表面方向的第一晶片和具有不同的第二表面取向和不同的第二表面方向的第二晶片顶部的第一表面取向接合; 形成通过所述第一晶片的开口到所述第二晶片; 以及在所述开口中形成与所述第一晶片的表面共面的区域，其中所述区域具有第二表面取向和所述第二表面方向。 半导体器件结构包括具有不同表面方向的至少两个有源区，每个有源区包括多个nFET和多个pFET中的一个，并且其中栅电极取向使得nFET和pFET基本上平行于每个 其他。
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公开(公告)号：US08215074B2
公开(公告)日：2012-07-10
申请号：US12026123
申请日：2008-02-05
IPC分类号： E04B2/00
CPC分类号： H01L21/0338 , B81B2203/0369 , B81C1/00031 , B81C2201/0149 , B81C2201/0198 , B82Y30/00 , H01L21/0337 , H01L51/0017 , Y10S977/882 , Y10S977/887 , Y10S977/888 , Y10T428/24479 , Y10T428/2457 , Y10T428/24612 , Y10T428/24736 , Y10T428/24802
摘要： In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.
摘要翻译： 在一个实施例中，包括大的六边形瓦片被分成三组，每组包含彼此分离的所有六边形瓦片的1/3。 每个组中的六边形瓦片的开口形成在模板层中，并且在每个开口内施加并组合一组自组装嵌段共聚物。 该过程重复三次以包含所有三组，导致在大面积上延伸的自对准图案。 在另一个实施例中，大面积被分成两个不重叠和互补组的矩形瓦片。 每个矩形区域的宽度小于自组装嵌段共聚物的顺序范围。 在每组中以顺序的方式形成自组装的自对准线和空间结构，使得在超过有序范围的大面积上形成线和空间图案。
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