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31.发明申请公开(公告)号：US20100250900A1
公开(公告)日：2010-09-30
申请号：US12409934
申请日：2009-03-24
IPC分类号： G06F9/30
CPC分类号： G06F9/3814 , G06F9/3838
摘要： An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions along with relative instruction to instruction dependency information. A mapper maps queue position data for instructions that dispatch to issue queue locations within the IU. The IU may test an issuing producer instruction against consumer instructions in the IU for queue position (QPOS) and register tag (RTAG) matches. A matching consumer instruction may issue in a successive manner in the case of a queue position match or in a next processor cycle in the case of a register tag match.
摘要翻译： 信息处理系统包括具有发布单元（IU）的处理器，该单元可对连续指令发布操作执行指令依赖性跟踪。 IU保持非移位问题队列（NSIQ）和移位发送队列（SIQ）指令以及与指令依赖信息的相关指令。 映射器映射队列位置数据，用于发送在IU内发出队列位置的指令。 IU可以根据IU中的消费者指令测试发出生产者指令的队列位置（QPOS）和注册标签（RTAG）匹配。 在队列位置匹配的情况下，或者在注册标签匹配的情况下，在下一个处理器周期中，匹配的消费者指令可以以连续的方式发布。
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32.发明授权Method and apparatus for preventing soft error accumulation in register arrays 有权用于防止寄存器阵列中的软错误累积的方法和装置公开(公告)号：US07774654B2
公开(公告)日：2010-08-10
申请号：US12051904
申请日：2008-03-20
申请人： Pradip Bose , Jude A. Rivers , Balaram Sinharoy , Victor Zyuban
发明人： Pradip Bose , Jude A. Rivers , Balaram Sinharoy , Victor Zyuban
IPC分类号： G06F11/00
CPC分类号： G06F11/004 , G06F11/3409 , G06F2201/88
摘要： A computer implemented method, apparatus, and computer usable program code for preventing soft error accumulation. A number of cycles between references to a register are counted. Instructions are injected that reference the register for preventing soft error accumulation in response to a determination that the number of cycles is greater than a threshold.
摘要翻译： 一种用于防止软错误累积的计算机实现的方法，装置和计算机可用程序代码。 对寄存器的引用之间的一些周期进行计数。 针对响应于循环数大于阈值的确定，注入参考寄存器以防止软错误累积的指令。
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公开(公告)号：US20090199170A1
公开(公告)日：2009-08-06
申请号：US12024191
申请日：2008-02-01
IPC分类号： G06F9/44
CPC分类号： G06F8/41 , G06F9/383 , G06F9/3851
摘要： A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. If executing a portion of the set of helper thread binaries results in the retrieval of data needed by the set of main thread binaries, then that retrieved data is utilized by the set of main thread binaries.
摘要翻译： 创建一组辅助线程二进制文件来检索一组主线程二进制文件使用的数据。 如果执行一组辅助线程二进制文件的一部分导致检索主线程二进制文件集所需的数据，那么该检索的数据由主线程二进制文件集合使用。
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34.发明申请METHOD AND SYSTEM FOR SOURCING DIFFERING AMOUNTS OF PREFETCH DATA IN RESPONSE TO DATA PREFETCH REQUESTS 失效用于根据数据预先要求采集预取数据的不同数据的方法和系统公开(公告)号：US20090198965A1
公开(公告)日：2009-08-06
申请号：US12024165
申请日：2008-02-01
IPC分类号： G06F9/312
CPC分类号： G06F9/383 , G06F9/30043 , G06F9/3455
摘要： According to a method of data processing, a memory controller receives a prefetch load request from a processor core of a data processing system. The prefetch load request specifies a requested line of data. In response to receipt of the prefetch load request, the memory controller determines by reference to a stream of demand requests how much data is to be supplied to the processor core in response to the prefetch load request. In response to the memory controller determining to provide less than all of the requested line of data, the memory controller provides less than all of the requested line of data to the processor core.
摘要翻译： 根据数据处理的方法，存储器控制器从数据处理系统的处理器核心接收预取负载请求。 预取加载请求指定所请求的数据行。 响应于接收到预取加载请求，存储器控制器通过参考需求请求流来确定响应于预取加载请求将多少数据提供给处理器核。 响应于存储器控制器确定提供少于全部所请求的数据行，存储器控制器将少于所有请求的数据行提供给处理器核。
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35.发明申请公开(公告)号：US20090198963A1
公开(公告)日：2009-08-06
申请号：US12024513
申请日：2008-02-01
CPC分类号： G06F9/30087 , G06F9/30032 , G06F9/3004 , G06F9/3834 , G06F9/3885 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A method within a data processing system by which a processor executes an asynchronous memory move (AMM) store (ST) instruction to complete a corresponding AMM operation in parallel with an ongoing (not yet completed), previously issued barrier operation. The processor receives the AMM ST instruction after executing the barrier operation (or SYNC instruction) and before the completion of the barrier operation or SYNC on the system fabric. The processor continues executing the AMM ST instruction, which performs a move in virtual address space and then triggers the generation of the AMM operation. The AMM operation proceeds while the barrier operation continues, independent of the processor. The processor stops further execution of all other memory access requests, excluding AMM ST instructions that are received after the barrier operation, but before completion of the barrier operation.
摘要翻译： 数据处理系统中的方法，通过该方法，处理器执行异步存储器移动（AMM）存储（ST）指令以与正在进行的（未完成）先前发布的屏障操作并行地完成对应的AMM操作。 执行屏障操作（或SYNC指令）后，在系统结构上完成屏障操作或SYNC之前，处理器接收AMM ST指令。 处理器继续执行AMM ST指令，其在虚拟地址空间中执行移动，然后触发AMM操作的生成。 无障碍操作继续进行，与处理器无关，AMM操作继续进行。 处理器停止所有其他存储器访问请求的进一步执行，排除在屏障操作之后但在屏障操作完成之前接收的AMM ST指令。
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公开(公告)号：US20090198906A1
公开(公告)日：2009-08-06
申请号：US12024260
申请日：2008-02-01
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0862 , G06F12/0897 , G06F2212/6026 , G06F2212/681
摘要： A technique for performing data prefetching using multi-level indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content that is included in a first data block (e.g., a first cache line of a memory) at the first memory address is then fetched. A second memory address is then determined based on the content at the first memory address. Content that is included in a second data block (e.g., a second cache line) at the second memory address is then fetched (e.g., from the memory or another memory). A third memory address is then determined based on the content at the second memory address. Finally, a third data block (e.g., a third cache line) that includes another pointer or data at the third memory address is fetched (e.g., from the memory or the another memory).
摘要翻译： 使用多级间接数据预取来执行数据预取的技术包括确定与数据预取指令相关联的指针的第一存储器地址。 然后取出包含在第一存储器地址的第一数据块（例如，存储器的第一高速缓存行）中的内容。 然后基于第一存储器地址处的内容来确定第二存储器地址。 包含在第二存储器地址的第二数据块（例如，第二高速缓存行）中的内容然后被取出（例如，从存储器或另一个存储器）。 然后基于第二存储器地址处的内容来确定第三存储器地址。 最后，取出（例如，从存储器或另一个存储器）中包含第三存储器地址处的另一指针或数据的第三数据块（例如，第三高速缓存行）。
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公开(公告)号：US20090198905A1
公开(公告)日：2009-08-06
申请号：US12024248
申请日：2008-02-01
IPC分类号： G06F12/02
CPC分类号： G06F12/0862 , G06F12/0897 , G06F12/1027 , G06F2212/6026
摘要： A technique for data prefetching using indirect addressing includes monitoring data pointer values, associated with an array, in an access stream to a memory. The technique determines whether a pattern exists in the data pointer values. A prefetch table is then populated with respective entries that correspond to respective array address/data pointer pairs based on a predicted pattern in the data pointer values. Respective data blocks (e.g., respective cache lines) are then prefetched (e.g., from the memory or another memory) based on the respective entries in the prefetch table.
摘要翻译： 使用间接寻址的数据预取技术包括在到存储器的访问流中监视与阵列相关联的数据指针值。 该技术确定数据指针值中是否存在模式。 然后基于数据指针值中的预测模式，填充与各个阵列地址/数据指针对相对应的条目的预取表。 然后，基于预取表中的相应条目，预取（例如，从存储器或另一存储器）分别的数据块（例如，相应的高速缓存行）。
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38.发明申请公开(公告)号：US20090198904A1
公开(公告)日：2009-08-06
申请号：US12024246
申请日：2008-02-01
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/1045 , G06F2212/6028
摘要： A technique for performing data prefetching using indirect addressing includes determining a first memory address of a pointer associated with a data prefetch instruction. Content, that is included in a first data block (e.g., a first cache line) of a memory, at the first memory address is then fetched. An offset is then added to the content of the memory at the first memory address to provide a first offset memory address. A second memory address is then determined based on the first offset memory address. A second data block (e.g., a second cache line) that includes data at the second memory address is then fetched (e.g., from the memory or another memory). A data prefetch instruction may be indicated by a unique operational code (opcode), a unique extended opcode, or a field (including one or more bits) in an instruction.
摘要翻译： 使用间接寻址执行数据预取的技术包括确定与数据预取指令相关联的指针的第一存储器地址。 然后取出包含在第一存储器地址的存储器的第一数据块（例如，第一高速缓存行）中的内容。 然后将偏移量添加到第一存储器地址处的存储器的内容以提供第一偏移存储器地址。 然后基于第一偏移存储器地址确定第二存储器地址。 包括第二存储器地址上的数据的第二数据块（例如，第二高速缓存行）然后被取出（例如，从存储器或另一个存储器）。 数据预取指令可以由指令中的唯一操作代码（操作码），唯一扩展操作码或字段（包括一个或多个位）来指示。
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公开(公告)号：US07484062B2
公开(公告)日：2009-01-27
申请号：US11316070
申请日：2005-12-22
申请人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
CPC分类号： G06F9/30032 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F12/0862 , G06F12/0888 , G06F12/0897 , G06F2212/6028
摘要： A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a start of a semi-synchronous memory copy operation. The semi-synchronous memory copy operation is checked for a given value in at least one cache injection bit. In response to the given value in the cache injection bit, a predefined number of lines of destination data is copied into at least one level of cache memory.
摘要翻译： 公开了一种基于半同步存储器复制指令中的信息将数据插入高速缓冲存储器的系统，方法和计算机。 该方法包括确定半同步存储器复制操作的开始。 在至少一个高速缓存注入位中检查给定值的半同步存储器复制操作。 响应于高速缓存注入位中的给定值，预定数量的目的地数据行被复制到至少一级的高速缓存存储器中。
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公开(公告)号：US07454585B2
公开(公告)日：2008-11-18
申请号：US11316663
申请日：2005-12-22
申请人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/3824
摘要： A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline.
摘要翻译： 公开了一种用于将数据从存储器的第一部分半数同步地复制到存储器的第二部分的系统，方法和计算机程序产品。 该方法包括在处理器中接收对半同步存储器复制操作的呼叫。 半同步存储器复制操作通过设置标志位来保持对应于存储器中的源位置的虚拟源地址和对应于存储器中的目标位置的虚拟目标地址的有效性的时间持续性。 该呼叫至少包括虚拟源地址，虚拟目标地址和标识要复制的字节数的指示符。 存储器复制操作被放置在队列中以由存储器控制器执行。 队列耦合到存储器控制器。 随着随后的指令从指令流水线可用，继续执行至少一个后续指令。
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