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61 条记录 (耗时 0.02 秒)

    Method for tuning a VCO using a phase lock loop
    31.
    发明授权
    Method for tuning a VCO using a phase lock loop 有权
    使用锁相环调谐VCO的方法

    公开(公告)号：US06545547B2

    公开(公告)日：2003-04-08

    申请号：US09929677

    申请日：2001-08-13

    申请人： Ahmed Reda Fridi ,  Abdellatif Bellaouar ,  Sherif Embabi

    发明人： Ahmed Reda Fridi ,  Abdellatif Bellaouar ,  Sherif Embabi

    IPC分类号： H03L700

    CPC分类号： H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/181 ,  H03L7/187 ,  H03L7/199

    摘要： A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without the need for charge pumps. A PLL synthesizer (300) using such a PLL design provides for very fast lock times by using an open loop step and a closed loop step. The hybrid PLL can achieve coarse tuning within four clock cycles, while minimizing any errors caused by the VCO non-linearity. Temperature tracking and compensation is also provided. A SAR implementation (100) and an interpolation tuning implementation (200) are also described.

    摘要翻译： 具有混合数字粗调制VCO调谐和VCO温度漂移补偿的非常快速的锁定整数N PLL提供了完全数字调谐方案，而不需要电荷泵。 使用这种PLL设计的PLL合成器（300）通过使用开环步骤和闭环步骤提供非常快的锁定时间。 混合PLL可以在四个时钟周期内实现粗调谐，同时最小化由VCO非线性引起的任何误差。 还提供温度跟踪和补偿。 还描述了SAR实现（100）和插值调谐实现（200）。

    Low power fractional pulse generation in frequency tracking multi-band fractional-N phase lock loop
    32.
    发明授权
    Low power fractional pulse generation in frequency tracking multi-band fractional-N phase lock loop 有权
    频率跟踪中的低功率小数脉冲产生多频带分数N相锁相环

    公开(公告)号：US06249685B1

    公开(公告)日：2001-06-19

    申请号：US09217242

    申请日：1998-12-21

    申请人： Khaled M. Sharaf ,  Abdellatif Bellaouar

    发明人： Khaled M. Sharaf ,  Abdellatif Bellaouar

    IPC分类号： H04B106

    CPC分类号： H03L7/0891 ,  H03L7/0802 ,  H03L7/1978

    摘要： Multi-band fractional-N PLL synthesizers with built-in spurious sideband compensation, which tracks the VCO output, tend to consume large amounts of power (as much as 10 times) due to the RF operation of the compensation circuitry. This patent introduces a dynamic power approach where the compensation circuitry is biased only during the fractional portion of the cycle. This technique provides the advantages of fractional-N synthesizers with spur suppression, such as higher speed and lower phase noise with ultra low power dissipation.

    摘要翻译： 由于补偿电路的RF操作，具有跟踪VCO输出的内置寄生边带补偿的多频带分数N PLL合成器倾向于消耗大量功率（多达10倍）。 该专利引入了一种动态功率方法，其中补偿电路仅在循环的小数部分期间被偏置。 该技术提供了具有杂散抑制的分数N合成器的优点，例如具有超低功耗的较高速度和较低相位噪声。

    Low-power direct digital frequency synthesizer architecture
    33.
    发明授权
    Low-power direct digital frequency synthesizer architecture 失效
    低功耗直接数字频率合成器架构

    公开(公告)号：US5999581A

    公开(公告)日：1999-12-07

    申请号：US537299

    申请日：1995-09-29

    申请人： Abdellatif Bellaouar ,  Michael S. Obrecht ,  Mohamed I. Elmasry

    发明人： Abdellatif Bellaouar ,  Michael S. Obrecht ,  Mohamed I. Elmasry

    IPC分类号： G06F1/035 ,  H04L23/00

    CPC分类号： G06F1/0356

    摘要： A direct digital frequency synthesizer for generating a digital sine or cosine function waveform receive digital input. Memory stores digital samples along portions of sine and cosine function waveforms. The memory outputs the digital samples in response to a first portion of the digital input. Control logic is responsive to the digital input and controls the output of the digital samples from the memory to allow digital samples along a complete cycle of the sine or cosine function waveform to be output even though only portions of the sine and cosine function waveforms are stored in the memory. A linear interpolator receives a second portion of the digital input and modifies digital samples output by the memory to generate intermediate digital samples between the digital samples stored in the memory to improve accuracy.

    摘要翻译： 用于产生数字正弦或余弦函数波形的直接数字频率合成器接收数字输入。 存储器沿着正弦和余弦函数波形的部分存储数字样本。 存储器响应于数字输入的第一部分输出数字采样。 控制逻辑响应于数字输入并且控制来自存储器的数字样本的输出，以允许输出正弦或余弦函数波形的完整周期的数字样本，即使只存储正弦和余弦函数波形的一部分 在记忆中 线性内插器接收数字输入的第二部分并且修改由存储器输出的数字样本，以在存储在存储器中的数字样本之间产生中间数字采样以提高精度。

    Closed-loop digital power control for a wireless transmitter
    35.
    发明授权
    Closed-loop digital power control for a wireless transmitter 有权
    无线发射机的闭环数字功率控制

    公开(公告)号：US08509290B2

    公开(公告)日：2013-08-13

    申请号：US12520448

    申请日：2007-12-21

    申请人： Abdellatif Bellaouar ,  Tajinder Manku

    发明人： Abdellatif Bellaouar ,  Tajinder Manku

    IPC分类号： H04B1/38

    CPC分类号： H03G3/3047 ,  H04B2001/0416

    摘要： A closed loop power output calibration system for variable power output wireless devices. The wireless device includes a wireless transceiver having a transmit core coupled to a discrete power amplifier. Power detection circuitry formed in the wireless transceiver provides a detected power level of the power amplifier, and a reference power level, both of which are converted to digital signals using existing I and Q signal analog to digital converters in the receiver core. The digital signals are processed to cancel power distortion and temperature effects to provide a resulting power feedback signal. Corrective control signals are generated in response to the power feedback signal relative to a desired power output level. The gain in the transmit core is then adjusted in response to the corrective control signals such that the power amplifier outputs the target output power level.

    摘要翻译： 一种用于可变功率输出无线设备的闭环功率输出校准系统。 无线设备包括具有耦合到分立功率放大器的发射芯的无线收发器。 在无线收发器中形成的功率检测电路提供功率放大器的检测功率电平和参考功率电平，两者都使用接收机核心中现有的I和Q信号模数转换器转换成数字信号。 处理数字信号以消除功率失真和温度影响，以提供最终的功率反馈信号。 响应于功率反馈信号相对于期望的功率输出电平产生校正控制信号。 然后响应于校正控制信号调整发送内核中的增益，使得功率放大器输出目标输出功率电平。

    LOW SUPPLY REGULATOR HAVING A HIGH POWER SUPPLY REJECTION RATIO
    36.
    发明申请
    LOW SUPPLY REGULATOR HAVING A HIGH POWER SUPPLY REJECTION RATIO 有权
    具有高电源抑制比的低电压调节器

    公开(公告)号：US20120256613A1

    公开(公告)日：2012-10-11

    申请号：US13081239

    申请日：2011-04-06

    申请人： Abdellatif Bellaouar ,  Arul Balasubramaniyan ,  Solti Peng

    发明人： Abdellatif Bellaouar ,  Arul Balasubramaniyan ,  Solti Peng

    IPC分类号： G05F3/02

    CPC分类号： H04B15/06

    摘要： A power supply noise rejection circuit for functional circuits, such as a voltage controlled oscillator (VCO). The power supply noise rejection circuit includes an isolation transistor connected to a voltage supply for providing an output current and voltage substantially free of noise across the full frequency range. A current source, a diode connected reference transistor with resistance means connected between its gate and drain terminals, and a dummy circuit serially connected between the voltage supply and ground generate a bias voltage that is applied to the gate of the isolation transistor. The dummy circuit mimics the DC characteristics of the functional circuit such that the output current tracks with process and temperature variations. The isolation transistor and the reference transistor can have negative threshold voltages, and the circuit can include bleed means for drawing current from the gate of the reference transistor and isolation transistor.

    摘要翻译： 用于诸如压控振荡器（VCO）的功能电路的电源噪声抑制电路。 电源噪声抑制电路包括连接到电压源的隔离晶体管，用于在整个频率范围内提供基本上没有噪声的输出电流和电压。 电流源，二极管连接的参考晶体管，其电阻装置连接在其栅极和漏极端子之间，并且串联连接在电压源和地之间的虚拟电路产生施加到隔离晶体管的栅极的偏置电压。 虚拟电路模拟功能电路的DC特性，使得输出电流跟踪过程和温度变化。 隔离晶体管和参考晶体管可以具有负阈值电压，并且该电路可以包括用于从参考晶体管和隔离晶体管的栅极引出电流的放电装置。

    Automatic IIP2 calibration architecture
    38.
    发明授权
    Automatic IIP2 calibration architecture 有权
    自动IIP2校准架构

    公开(公告)号：US07742747B2

    公开(公告)日：2010-06-22

    申请号：US11626964

    申请日：2007-01-25

    申请人： Tajinder Manku ,  Abdellatif Bellaouar ,  Alan Holden ,  Hamid R. Safiri

    发明人： Tajinder Manku ,  Abdellatif Bellaouar ,  Alan Holden ,  Hamid R. Safiri

    IPC分类号： H04B1/04 ,  H04K3/00

    CPC分类号： H04B1/12 ,  H03D2200/0045 ,  H04B17/21

    摘要： An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.

    摘要翻译： 公开了一种用于无线收发器的综合自动IIP2校准架构。 该架构使得无线收发器能够生成具有最小附加电路的具有二阶音调的测试射频（RF）信号。 特别地，使用本机收发器电路和测试适配器电路的组合产生测试RF信号。 本地收发器电路是在收发器芯片上实现的用于在正常操作期间执行本机收发器功能的那些电路，其可用于产生测试（RF）信号。 测试适配器电路被添加到收发器芯片中，更具体地被添加到本地电路，用于使得本机电路能够以自测试操作模式生成测试RF信号。 用于实现特定的IIP2最小化方案的电路可以在自检操作模式下在收发器芯片中包括在自动IIP2校准中。

    DIGITAL LINEAR TRANSMITTER ARCHITECTURE
    39.
    发明申请
    DIGITAL LINEAR TRANSMITTER ARCHITECTURE 有权
    数字线性发射机架构

    公开(公告)号：US20100027711A1

    公开(公告)日：2010-02-04

    申请号：US12520486

    申请日：2007-12-14

    申请人： Tajinder Manku ,  Abdellatif Bellaouar

    发明人： Tajinder Manku ,  Abdellatif Bellaouar

    IPC分类号： H04L27/00 ,  H03M1/66

    CPC分类号： H03M1/68 ,  H03M1/745 ,  H03M3/50 ,  H03M7/3004

    摘要： A digital linear transmitter for digital to analog conversion of a radio frequency signal. The transmitter includes a delta sigma (ΔΣ) digital to analog converter (DAC) and a weighted signal digital to analog converter in the transmit path of a wireless device to reduce reliance on relatively large analog components. The ΔΣ DAC converts the lowest significant bits of the oversampled signal while the weighted signal digital to analog converter converts the highest significant bits of the oversampled signal. The transmitter core includes components for providing an oversampled modulated digital signal which is then subjected to first order filtering of the oversampled signal prior to generating a corresponding analog signal. The apparatus and method reduces analog components and increases digital components in transmitter core architecture of wireless RF devices.

    摘要翻译： 一种用于数字到模拟转换射频信号的数字线性发射机。 发射机在无线设备的发射路径中包括Δ西格玛（DeltaSigma）数模转换器（DAC）和加权信号数模转换器，以减少对相对大的模拟组件的依赖。 DeltaSigma DAC转换过采样信号的最低有效位，而加权信号数模转换器转换过采样信号的最高有效位。 发射机核心包括用于提供过采样的调制数字信号的组件，然后在产生相应的模拟信号之前对过采样信号进行一阶滤波。 该装置和方法减少了模拟组件并增加了无线RF设备的发射机核心架构中的数字组件。

    CLOSED-LOOP DIGITAL POWER CONTROL FOR A WIRELESS TRANSMITTER
    40.
    发明申请
    CLOSED-LOOP DIGITAL POWER CONTROL FOR A WIRELESS TRANSMITTER 有权
    无线发射机闭环数字功率控制

    公开(公告)号：US20100027596A1

    公开(公告)日：2010-02-04

    申请号：US12520448

    申请日：2007-12-21

    申请人： Abdellatif Bellaouar ,  Tajinder Manku

    发明人： Abdellatif Bellaouar ,  Tajinder Manku

    IPC分类号： H04B1/38

    CPC分类号： H03G3/3047 ,  H04B2001/0416

    摘要： A closed loop power output calibration system for variable power output wireless devices. The wireless device includes a wireless transceiver having a transmit core coupled to a discrete power amplifier. Power detection circuitry formed in the wireless transceiver provides a detected power level of the power amplifier, and a reference power level, both of which are converted to digital signals using existing I and Q signal analog to digital converters in the receiver core. The digital signals are processed to cancel power distortion and temperature effects to provide a resulting power feedback signal. Corrective control signals are generated in response to the power feedback signal relative to a desired power output level. The gain in the transmit core is then adjusted in response to the corrective control signals such that the power amplifier outputs the target output power level.

    摘要翻译： 一种用于可变功率输出无线设备的闭环功率输出校准系统。 无线设备包括具有耦合到分立功率放大器的发射芯的无线收发器。 在无线收发器中形成的功率检测电路提供功率放大器的检测功率电平和参考功率电平，两者都使用接收机核心中现有的I和Q信号模数转换器转换成数字信号。 处理数字信号以消除功率失真和温度影响，以提供最终的功率反馈信号。 响应于功率反馈信号相对于期望的功率输出电平产生校正控制信号。 然后响应于校正控制信号调整发送内核中的增益，使得功率放大器输出目标输出功率电平。