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公开(公告)号：US07693236B2
公开(公告)日：2010-04-06
申请号：US09851191
申请日：2001-05-08
IPC分类号： H03K9/00
CPC分类号： H04L27/2332
摘要： An RF receiver apparatus (31) is provided physically separately from a cooperating baseband processor apparatus (32). The RF receiver includes a mixer circuit (33) and an analog IF-to-digital baseband converter (34) formed on an integrated circuit. Sampling frequencies of the analog IF-to-digital baseband converter are controlled by the RF receiver apparatus.
摘要翻译： 与合作的基带处理器装置（32）物理上分开地提供RF接收机装置（31）。 RF接收机包括形成在集成电路上的混频器电路（33）和模拟IF到数字基带转换器（34）。 模拟IF到数字基带转换器的采样频率由RF接收机设备控制。
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公开(公告)号：US07110732B2
公开(公告)日：2006-09-19
申请号：US10102428
申请日：2002-03-19
申请人： Mohamed A. I. Mostafa , Sherif Embabi , Moderage C. Fernando , Wing Kan Chan , Charles Gore, Jr.
发明人： Mohamed A. I. Mostafa , Sherif Embabi , Moderage C. Fernando , Wing Kan Chan , Charles Gore, Jr.
CPC分类号： H04B1/0025 , H04B1/0003 , H04B1/28 , H04B1/30
摘要： A subsampling receiver (50, 50′, 50″) for converting an RF signal to baseband is disclosed. The subsampling receiver (50, 50′, 50″) may be implemented into a wireless communications device (40), such as a wireless telephone handset. In one disclosed embodiment, the receiver (50) includes a sample and hold circuit (80) that samples a bandpass filtered input modulated signal at the subsampling frequency (fs) that is well below the RF carrier frequency but twice the bandwidth (BW) of the payload; the sampled signal is digitized, and applied to two digital mixers (85I, 85Q) to produce in-phase and quadrature components (I,Q) of the payload. In another embodiment, the receiver (50′) includes two sample and hold circuits (96I, 96Q) to sample the filtered signal at different phases of the sampling frequency, to produce the in-phase and quadrature digital components. In a third embodiment, the receiver (50″) includes an analog mixer (116) to downconvert the RF input to an intermediate frequency, prior to digitization and digital mixing at quadrature phase.
摘要翻译： 公开了一种用于将RF信号转换为基带的子采样接收器（50,50'，50“）。 子采样接收器（50,50'，50“）可以被实现为诸如无线电话手机的无线通信设备（40）。 在一个公开的实施例中，接收器（50）包括采样和保持电路（80），采样和保持电路（80）采用非常低于RF载波频率的子采样频率（f SUB）的带通滤波的输入调制信号 但是有效载荷的带宽（BW）的两倍; 采样信号被数字化，并被应用于两个数字混频器（85 I，85 Q），以产生有效载荷的同相和正交分量（I，Q）。 在另一个实施例中，接收器（50'）包括两个采样和保持电路（96 I，96 Q），以在采样频率的不同相位采样经滤波的信号，以产生同相和正交数字分量。 在第三实施例中，接收器（50“）包括在数字化之前将RF输入下变频到中频的模拟混频器（116），并且在正交相位处进行数字混频。
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公开(公告)号：US06545547B2
公开(公告)日：2003-04-08
申请号：US09929677
申请日：2001-08-13
IPC分类号： H03L700
摘要： A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without the need for charge pumps. A PLL synthesizer (300) using such a PLL design provides for very fast lock times by using an open loop step and a closed loop step. The hybrid PLL can achieve coarse tuning within four clock cycles, while minimizing any errors caused by the VCO non-linearity. Temperature tracking and compensation is also provided. A SAR implementation (100) and an interpolation tuning implementation (200) are also described.
摘要翻译： 具有混合数字粗调制VCO调谐和VCO温度漂移补偿的非常快速的锁定整数N PLL提供了完全数字调谐方案，而不需要电荷泵。 使用这种PLL设计的PLL合成器（300）通过使用开环步骤和闭环步骤提供非常快的锁定时间。 混合PLL可以在四个时钟周期内实现粗调谐，同时最小化由VCO非线性引起的任何误差。 还提供温度跟踪和补偿。 还描述了SAR实现（100）和插值调谐实现（200）。
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4.发明申请System for reducing second order intermodulation products from differential circuits 有权用于从差分电路减少二阶互调产物的系统公开(公告)号：US20070132500A1
公开(公告)日：2007-06-14
申请号：US11298667
申请日：2005-12-12
IPC分类号： G06F7/44
CPC分类号： H03D7/1441 , H03D7/1433 , H03D7/1458 , H03D7/1466 , H03D2200/0047 , H03D2200/0088
摘要： A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated. The switching transistors of the mixer circuit can be maintained at minimal dimensions to reduce switching signal drive loading, resulting in lower power consumption and higher operating frequencies than if larger switching transistors were used.
摘要翻译： 一种具有用于平衡两个输出路径的电气特性的失配校正电路的无源CMOS差分混频器电路。 一旦差分电路的输出路径平衡或尽可能匹配，可以抑制二阶互调乘积的产生或至少降低到可接受的水平。 失配校正电路接收数字偏移信号，并产生一个或多个电压信号以选择性地施加到无源差分混频器电路的信号路径。 电压信号可以调节施加到所选晶体管的体积端子的反向栅极偏置电压以调整其阈值电压，或者可以将电压信号调整为直接施加到选定信号路径的共模电压。 由于差分混频器电路是无源的，所以不产生直流电流对噪声的贡献。 混合电路的开关晶体管可以维持在最小的尺寸以减少开关信号驱动负载，导致比使用更大的开关晶体管时更低的功耗和更高的工作频率。
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公开(公告)号：US06646498B2
公开(公告)日：2003-11-11
申请号：US10026280
申请日：2001-12-18
IPC分类号： H03K500
CPC分类号： H03H11/1213 , H03B5/04 , H03B5/24 , H03H11/1286
摘要： An integrated circuit (ICT) comprising a filter (50). The filter comprises an input (&ugr;in+) for receiving an input signal and an output (56) for producing an output signal having a frequency cutoff point. The filter further comprises at least one resistor network (RN1) coupled between the input and the output. The resistor network comprises a first non-switched resistance (R1.1) and a first resistance series connection connected in parallel with the first non-switched resistance. The first resistance series connection comprises a switched resistance (R1.2) connected in series with a source/drain path of a switching transistor (TRR1.2), the switching transistor having a gate for receiving a control signal. The frequency cutoff point is adjustable in response to the control signal. Additionally, the switched resistance has a first resistance and the switching transistor has an on-resistance. Further, the on-resistance is at least 20 percent of the total of the first resistance and the on-resistance.
摘要翻译： 一种包括滤波器（50）的集成电路（ICT）。 滤波器包括用于接收输入信号的输入（upsilonin +）和用于产生具有频率截止点的输出信号的输出（56）。 滤波器还包括耦合在输入和输出之间的至少一个电阻网络（RN1）。 电阻网络包括与第一非开关电阻并联连接的第一非开关电阻（R1.1）和第一电阻串联连接。 第一电阻串联包括与开关晶体管（TRR1.2）的源极/漏极路径串联连接的开关电阻（R1.2），开关晶体管具有用于接收控制信号的栅极。 频率截止点可根据控制信号进行调节。 此外，开关电阻具有第一电阻，并且开关晶体管具有导通电阻。 此外，导通电阻是第一电阻和导通电阻的总和的至少20％。
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