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公开(公告)号：US06545547B2
公开(公告)日：2003-04-08
申请号：US09929677
申请日：2001-08-13
IPC分类号： H03L700
摘要： A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without the need for charge pumps. A PLL synthesizer (300) using such a PLL design provides for very fast lock times by using an open loop step and a closed loop step. The hybrid PLL can achieve coarse tuning within four clock cycles, while minimizing any errors caused by the VCO non-linearity. Temperature tracking and compensation is also provided. A SAR implementation (100) and an interpolation tuning implementation (200) are also described.
摘要翻译： 具有混合数字粗调制VCO调谐和VCO温度漂移补偿的非常快速的锁定整数N PLL提供了完全数字调谐方案，而不需要电荷泵。 使用这种PLL设计的PLL合成器（300）通过使用开环步骤和闭环步骤提供非常快的锁定时间。 混合PLL可以在四个时钟周期内实现粗调谐，同时最小化由VCO非线性引起的任何误差。 还提供温度跟踪和补偿。 还描述了SAR实现（100）和插值调谐实现（200）。
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2.发明授权Fractional-spurs suppression scheme in frequency tracking multi-band fractional-N phase lock loop 有权频率跟踪多频带分数N相锁相环中的小数马刺抑制方案公开(公告)号：US06308049B1
公开(公告)日：2001-10-23
申请号：US09217222
申请日：1998-12-21
IPC分类号： H04B140
CPC分类号： H03L7/1976 , H03L7/0891
摘要： The present invention discusses fractional compensation timing circuitry (15) to track a VCO output frequency, fO, and provide highly effective error cancellation in a fractional-N PLL synthesizer. This output frequency tracking is used to suppress spurious sidebands, commonly known as spurs, in both fixed-band and multi-band wireless transceiver applications which use fractional-N PLL synthesizers. Some of the critical parameters which benefit from this type of PLL include switching time, phase noise, and reference feed-through.
摘要翻译： 本发明讨论了用于跟踪VCO输出频率f0的分数补偿定时电路（15），并且在分数N PLL合成器中提供高效的误差消除。 该输出频率跟踪用于在使用分数N PLL合成器的固定频带和多频带无线收发器应用中抑制通常称为杂散的杂散边带。 从这种类型的PLL中受益的一些关键参数包括切换时间，相位噪声和参考馈通。
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3.发明申请System for reducing second order intermodulation products from differential circuits 有权用于从差分电路减少二阶互调产物的系统公开(公告)号：US20070132500A1
公开(公告)日：2007-06-14
申请号：US11298667
申请日：2005-12-12
IPC分类号： G06F7/44
CPC分类号： H03D7/1441 , H03D7/1433 , H03D7/1458 , H03D7/1466 , H03D2200/0047 , H03D2200/0088
摘要： A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated. The switching transistors of the mixer circuit can be maintained at minimal dimensions to reduce switching signal drive loading, resulting in lower power consumption and higher operating frequencies than if larger switching transistors were used.
摘要翻译： 一种具有用于平衡两个输出路径的电气特性的失配校正电路的无源CMOS差分混频器电路。 一旦差分电路的输出路径平衡或尽可能匹配，可以抑制二阶互调乘积的产生或至少降低到可接受的水平。 失配校正电路接收数字偏移信号，并产生一个或多个电压信号以选择性地施加到无源差分混频器电路的信号路径。 电压信号可以调节施加到所选晶体管的体积端子的反向栅极偏置电压以调整其阈值电压，或者可以将电压信号调整为直接施加到选定信号路径的共模电压。 由于差分混频器电路是无源的，所以不产生直流电流对噪声的贡献。 混合电路的开关晶体管可以维持在最小的尺寸以减少开关信号驱动负载，导致比使用更大的开关晶体管时更低的功耗和更高的工作频率。
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公开(公告)号：US06646498B2
公开(公告)日：2003-11-11
申请号：US10026280
申请日：2001-12-18
IPC分类号： H03K500
CPC分类号： H03H11/1213 , H03B5/04 , H03B5/24 , H03H11/1286
摘要： An integrated circuit (ICT) comprising a filter (50). The filter comprises an input (&ugr;in+) for receiving an input signal and an output (56) for producing an output signal having a frequency cutoff point. The filter further comprises at least one resistor network (RN1) coupled between the input and the output. The resistor network comprises a first non-switched resistance (R1.1) and a first resistance series connection connected in parallel with the first non-switched resistance. The first resistance series connection comprises a switched resistance (R1.2) connected in series with a source/drain path of a switching transistor (TRR1.2), the switching transistor having a gate for receiving a control signal. The frequency cutoff point is adjustable in response to the control signal. Additionally, the switched resistance has a first resistance and the switching transistor has an on-resistance. Further, the on-resistance is at least 20 percent of the total of the first resistance and the on-resistance.
摘要翻译： 一种包括滤波器（50）的集成电路（ICT）。 滤波器包括用于接收输入信号的输入（upsilonin +）和用于产生具有频率截止点的输出信号的输出（56）。 滤波器还包括耦合在输入和输出之间的至少一个电阻网络（RN1）。 电阻网络包括与第一非开关电阻并联连接的第一非开关电阻（R1.1）和第一电阻串联连接。 第一电阻串联包括与开关晶体管（TRR1.2）的源极/漏极路径串联连接的开关电阻（R1.2），开关晶体管具有用于接收控制信号的栅极。 频率截止点可根据控制信号进行调节。 此外，开关电阻具有第一电阻，并且开关晶体管具有导通电阻。 此外，导通电阻是第一电阻和导通电阻的总和的至少20％。
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公开(公告)号：US08669754B2
公开(公告)日：2014-03-11
申请号：US13081239
申请日：2011-04-06
IPC分类号： G05F3/16
CPC分类号： H04B15/06
摘要： A power supply noise rejection circuit for functional circuits, such as a voltage controlled oscillator (VCO). The power supply noise rejection circuit includes an isolation transistor connected to a voltage supply for providing an output current and voltage substantially free of noise across the full frequency range. A current source, a diode connected reference transistor with resistance means connected between its gate and drain terminals, and a dummy circuit serially connected between the voltage supply and ground generate a bias voltage that is applied to the gate of the isolation transistor. The dummy circuit mimics the DC characteristics of the functional circuit such that the output current tracks with process and temperature variations. The isolation transistor and the reference transistor can have negative threshold voltages, and the circuit can include bleed means for drawing current from the gate of the reference transistor and isolation transistor.
摘要翻译： 用于诸如压控振荡器（VCO）的功能电路的电源噪声抑制电路。 电源噪声抑制电路包括连接到电压源的隔离晶体管，用于在整个频率范围内提供基本上没有噪声的输出电流和电压。 电流源，二极管连接的参考晶体管，其电阻装置连接在其栅极和漏极端子之间，并且串联连接在电压源和地之间的虚拟电路产生施加到隔离晶体管的栅极的偏置电压。 虚拟电路模拟功能电路的DC特性，使得输出电流跟踪过程和温度变化。 隔离晶体管和参考晶体管可以具有负阈值电压，并且该电路可以包括用于从参考晶体管和隔离晶体管的栅极引出电流的放电装置。
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公开(公告)号：US20100029228A1
公开(公告)日：2010-02-04
申请号：US12520518
申请日：2007-12-20
申请人： Alan Holden , Hamid Safiri , Michel J.G.J.P. Frechette , Sherif H.K. Embabi , Abdellatif Bellaouar , Stephen Arnold Devison , Tajinder Manku
发明人： Alan Holden , Hamid Safiri , Michel J.G.J.P. Frechette , Sherif H.K. Embabi , Abdellatif Bellaouar , Stephen Arnold Devison , Tajinder Manku
IPC分类号： H04B1/04
CPC分类号： H03G3/3047
摘要： A power ramping circuit for use in the transmit path of a radio frequency (RF) circuit. The power ramping circuit includes parallel connected transistors used as logarithmic resistor attenuators for adjusting current to a mixer circuit in the transmit path. The parallel connected transistors can be sized differently, and are sequentially turned off to gradually increase the current provided to the mixer circuit. A ramp control circuit controls the parallel connected transistors in response to either an analog signal or a digital signal.
摘要翻译： 一种用于射频（RF）电路的发射路径的功率斜坡电路。 功率斜坡电路包括并联的晶体管，用作对数电阻衰减器，用于调节到发射路径中的混频器电路的电流。 并联连接的晶体管的尺寸可以不同，并被依次关闭，以逐渐增加提供给混频器电路的电流。 斜坡控制电路响应于模拟信号或数字信号来控制并联的晶体管。
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7.发明授权公开(公告)号：US07359684B2
公开(公告)日：2008-04-15
申请号：US10012869
申请日：2001-11-06
CPC分类号： H04B1/26 , H04B1/0475 , H04B2001/0491
摘要： A wireless communication device (UST), comprising an input for receiving baseband data (I, Q) in a first signal having a first frequency. The device also comprises circuitry (681, 682) for increasing the first frequency, to form a second signal having a second frequency, in response to a first frequency reference signal (IF2), and the device comprises circuitry (74) for increasing the second frequency, to form a third signal having a third frequency, in response to a second frequency reference signal (LO2). Lastly, the device comprises an antenna (ATU2) for transmitting the baseband data at a final transmission frequency selected as a band within a predetermined set of frequency bands. With reference to the preceding, the first frequency reference signal and the second frequency reference signal are variable and are selected in response to the final transmission frequency which is a particular band selected as a different band at different times and from the predetermined set of frequency bands.
摘要翻译： 一种无线通信设备（UST），包括用于在具有第一频率的第一信号中接收基带数据（I，Q）的输入。 该装置还包括用于增加第一频率的电路（68 1，68 2 2），以响应于第一频率参考信号形成具有第二频率的第二信号 （IF 2 2），并且该装置包括用于响应于第二频率参考信号（LO 2）而增加第二频率以形成具有第三频率的第三信号的电路（74） ）。 最后，该设备包括用于以选定为预定频带组内的频带的最终传输频率发送基带数据的天线（ATU 2）。 参考前述，第一频率参考信号和第二频率参考信号是可变的，并且是响应于作为在不同时间被选择为不同频带的特定频带的最终发射频率和从预定频带组中选择的 。
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公开(公告)号：US20060055579A1
公开(公告)日：2006-03-16
申请号：US11203717
申请日：2005-08-15
IPC分类号： H03M1/12
摘要： A receiver 100 is provided. The receiver 100 comprises an in-phase analog-to-digital converter 112 operable to detect a saturation condition of the in-phase analog-to-digital converter 112 and to adjust the amplitude of a in-phase signal processed by the in-phase analog-to-digital converter 112 to remove the in-phase analog-to-digital converter 112 from the saturation condition and a in-phase digital filter 114 operable to adjust a gain applied to a digital input to the in-phase digital filter 114 from the in-phase analog-to-digital converter 112, the adjustment of the gain substantially inversely proportional to the adjustment of the amplitude of the in-phase signal processed by the in-phase analog-to-digital converter 112. In an embodiment, the receiver 100 also comprises a quadrature path that is substantially similar to the in-phase path, and the in-phase path and the quadrature path comprise a direct conversion receiver. In an embodiment, the in-phase analog-to-digital converter 112 and the in-phase digital filter 114 comprise an intermediate frequency receiver.
摘要翻译： 提供接收器100。 接收器100包括同相模拟数字转换器112，其可操作以检测同相模数转换器112的饱和状态，并调整由同相模数转换器112处理的同相信号的振幅 模数转换器112以从饱和状态除去同相模数转换器112;以及同相数字滤波器114，其可操作以调整施加到同相数字滤波器114的数字输入的增益 来自同相模数转换器112的增益基本上与由同相模数转换器112处理的同相信号的振幅的调整成反比地成比例。在一个实施例中 接收器100还包括基本上类似于同相路径的正交路径，并且同相路径和正交路径包括直接转换接收器。 在一个实施例中，同相模数转换器112和同相数字滤波器114包括中频接收器。
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9.发明授权Programmable linear-in-dB or linear bias current source and methods to implement current reduction in a PA driver with built-in current steering VGA 有权可编程线性dB或线性偏置电流源以及使用内置电流转向VGA实现PA驱动器电流降低的方法公开(公告)号：US06985028B2
公开(公告)日：2006-01-10
申请号：US10689311
申请日：2003-10-20
申请人： See Taur Lee , Abdellatif Bellaouar
发明人： See Taur Lee , Abdellatif Bellaouar
IPC分类号： G05F3/02
CPC分类号： G05F3/262
摘要： Programmable linear-in-dB or linear bias current source with respect to an input voltage is provided. The linear-in-dB or linear bias current may be clipped at a minimum current level, a maximum current level, or a combination thereof. Preferably, the minimum and maximum current levels are determined by the use of one or more constant current sources. The constant current sources limit the amount of voltage applied to the gates of one or more transistors, which in turn control the output current. The use of the circuit may be used to generate linear or reverse-linear current levels with respect to an input voltage. The output of the current generator may be used as an input to a power-amplifier driver, for example.
摘要翻译： 提供了相对于输入电压的可编程线性dB或线性偏置电流源。 线性dB或线性偏置电流可以以最小电流电平，最大电流电平或其组合进行钳位。 优选地，最小和最大电流水平通过使用一个或多个恒定电流源来确定。 恒定电流源限制施加到一个或多个晶体管的栅极的电压的量，其又控制输出电流。 电路的使用可用于相对于输入电压产生线性或反向线性电流水平。 电流发生器的输出可以例如用作功率放大器驱动器的输入。
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公开(公告)号：US06492840B1
公开(公告)日：2002-12-10
申请号：US09669021
申请日：2000-09-25
申请人： Abdellatif Bellaouar
发明人： Abdellatif Bellaouar
IPC分类号： H03K1700
CPC分类号： H03K19/086 , H03K19/09432
摘要： A new family of current mode logic (CML) gates (14) which, in one embodiment includes OR/NOR and AND/NAND gates, as well as more complex logic functions. The circuit uses a complementary signal to drive the gate of a feedback transistor (19) which has the effect of pseudo differential operation. Although it uses only single-ended inputs (A, B), because of this feedback aspect, the circuit has many of the advantages of a differential circuit such as low-voltage operation, higher immunity to noise, and less sensitivity to parasitic elements.
摘要翻译： 一种新的电流模式逻辑（CML）门（14），其在一个实施例中包括OR / NOR和AND / NAND门，以及更复杂的逻辑功能。 该电路使用互补信号来驱动具有伪差动作用的反馈晶体管（19）的栅极。 尽管它仅使用单端输入（A，B），由于这种反馈方面，该电路具有差分电路的许多优点，例如低电压操作，较高的抗噪声能力和较小的对寄生元件的灵敏度。
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