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31.发明申请PROCESSOR AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR MULTIPLICATION OF LARGE OPERANDS 有权用于实施大规模操作的指导性支持的处理器和方法公开(公告)号：US20100325188A1
公开(公告)日：2010-12-23
申请号：US12488372
申请日：2009-06-19
IPC分类号： G06F7/52
CPC分类号： G06F7/4876 , G06F2207/382
摘要： A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a hardware multiplier datapath circuit, where the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M. In response to receiving a single instance of a large-operand multiplication instruction defined within the ISA, wherein at least one of the operands of the large-operand multiplication instruction includes more than the maximum number of bits M, the instruction execution unit is configured to multiply operands of the large-operand multiplication instruction within the hardware multiplier datapath circuit to determine a result of the large-operand multiplication instruction without execution of programmer-selected instructions within the ISA other than the large-operand multiplication instruction.
摘要翻译： 包括用于实现大操作数乘法的指令支持的处理器可以从定义的指令集架构（ISA）发出用于执行编程器可选择指令的执行。 处理器可以包括指令执行单元，其包括硬件乘法器数据路径电路，其中硬件乘法器数据路径电路被配置为对具有最大位数M的操作数进行乘法。响应于接收到在其中定义的大操作数乘法指令的单个实例 所述ISA，其中所述大操作数乘法指令的操作数中的至少一个包括多于所述最大位数M，所述指令执行单元被配置为将所述大操作数乘法指令在所述硬件乘法器数据通路电路内的操作数乘以 确定大操作数乘法指令的结果，而不在大操作数乘法指令之外执行ISA内的编程器选择指令。
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公开(公告)号：US20100274992A1
公开(公告)日：2010-10-28
申请号：US12428459
申请日：2009-04-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/30032 , G06F9/30109 , G06F9/384 , G06F9/3851 , G06F9/3861
摘要： Techniques for handling dependency conditions, including evil twin conditions, are disclosed herein. An instruction may designate a source register comprising two portions. The source register may be a double-precision register and its two portions may be single-precision portions, each specified as destinations by two other single-precision instructions. Execution of these two single-precision instructions, especially on a register renaming machine, may result in the appropriate values for the two portions of the source register being stored in different physical locations, which can complicate execution of an instruction stream. In response to detecting a potential dependency, one or more instructions may be inserted in an instruction stream to enable the appropriate values to be stored within one physical double precision register, eliminating an actual or potential evil twin dependency. Embodiments including a compiler that inserts instructions in a generated instruction stream to eliminate dependency conditions are also contemplated.
摘要翻译： 用于处理依赖条件的技术，包括邪恶的双重条件。 指令可以指定包括两个部分的源寄存器。 源寄存器可以是双精度寄存器，其两部分可以是单精度部分，每一部分由两个其他单精度指令指定为目标。 执行这两个单精度指令，特别是在寄存器重命名机上，可能会导致源寄存器的两个部分的适当值存储在不同的物理位置，这会使指令流的执行变得复杂。 响应于检测到潜在依赖性，可以在指令流中插入一个或多个指令，以使适当的值存储在一个物理双精度寄存器中，从而消除实际或潜在的恶性倚靠。 包括编译器的实施例也包括在生成的指令流中插入指令以消除依赖条件的编译器。
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公开(公告)号：US07591385B2
公开(公告)日：2009-09-22
申请号：US11568621
申请日：2005-05-06
申请人： Jeffrey S. Brooks
发明人： Jeffrey S. Brooks
IPC分类号： A47F7/00
CPC分类号： B25H3/04 , A47F5/0846
摘要： A system for holding one or more implements. The system includes a wall-mounted rail having a channel-track extending lengthwise of the rail, and an implement holder having a track-engaging element slidable in the channel-track to a selected position on the rail. Fastener holes are spaced at intervals along the bottom wall of the channel-track for receiving one or more rail fasteners to mount the rail. One implement holder comprises a jar assembly which includes a jar for storing items and a bracket mountable on the rail for holding the jar. Other implement holders may also be used, including an implement holder with a snap-lock fastener for releasable snap-fastening interconnection with the rail. A support places the holder at a different position relative to the rail. A wall mounted bracket may be used for supporting the holder.
摘要翻译： 一种用于保持一个或多个工具的系统。 该系统包括壁挂式导轨，其具有沿导轨纵向延伸的通道轨道，以及具有轨道接合元件的工具保持器，轨道接合元件可在通道轨道中滑动到轨道上的选定位置。 紧固件孔沿着通道轨道的底壁间隔开，用于接收一个或多个轨道紧固件以安装轨道。 一个器具保持器包括一个罐组件，其包括用于存放物品的罐和可安装在轨道上用于保持罐的支架。 还可以使用其它器具保持器，包括具有用于与轨道可释放的卡扣紧固互连的卡扣紧固件的工具保持器。 支架将支架放置在相对于导轨的不同位置。 壁挂式支架可用于支撑支架。
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公开(公告)号：US07523330B2
公开(公告)日：2009-04-21
申请号：US10881246
申请日：2004-06-30
IPC分类号： G06F1/26
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G06F9/3851 , Y02D10/128 , Y02D10/171
摘要： A method and apparatus for controlling power consumption in a multi-threaded processor. In one embodiment, the processor includes at least one logic unit for processing instructions. The logic unit includes a plurality of positions, wherein each of the plurality of positions corresponds to at least one instruction thread. Clock signals may be provided to the logic unit via a clock gating unit. The clock gating unit is configured to inhibit a clock signal from being provided to a corresponding one of the thread positions when no instruction thread is active for that position. The inhibiting of the clock signal for an inactive thread position may reduce power consumption by the processor.
摘要翻译： 一种用于控制多线程处理器中的功耗的方法和装置。 在一个实施例中，处理器包括用于处理指令的至少一个逻辑单元。 逻辑单元包括多个位置，其中多个位置中的每一个对应于至少一个指令线程。 时钟信号可以经由时钟门控单元提供给逻辑单元。 时钟门控单元被配置为当没有指令线程对于该位置有效时，禁止将时钟信号提供给相应的一个线程位置。 禁止线程位置的时钟信号的抑制可能会降低处理器的功耗。
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公开(公告)号：US07051452B2
公开(公告)日：2006-05-30
申请号：US10685059
申请日：2003-10-14
申请人： Jeffrey S. Brooks
发明人： Jeffrey S. Brooks
IPC分类号： A61B5/107
摘要： A system and method for measuring the size of a person's foot so that properly sized shoes can be selected. The measuring system has a support surface having a transparent window, and a fixture positioned over the transparent window for receiving a foot to be scanned. The measuring system also includes an imaging device for scanning the foot in the fixture through the window to produce an image of a bottom surface of the foot superimposed on foot measuring indicia. In one embodiment, the fixture is shaped like a shoe. The person can print the image and use the image to select a properly sized pair of shoes.
摘要翻译： 一种用于测量人脚尺寸的系统和方法，以便可以选择适当尺寸的鞋。 测量系统具有支撑表面，其具有透明窗口，以及位于透明窗口上方的用于接收待扫描的脚的固定器。 该测量系统还包括一个成像装置，用于通过窗口扫描固定装置中的脚，以产生叠加在足部测量标记上的足部底面的图像。 在一个实施例中，固定装置形状如鞋。 该人可以打印图像并使用图像来选择适当尺寸的一双鞋。
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公开(公告)号：US06854198B2
公开(公告)日：2005-02-15
申请号：US09855890
申请日：2001-05-15
申请人： Jeffrey S. Brooks
发明人： Jeffrey S. Brooks
CPC分类号： A43B7/141 , A43B1/0027 , A43B1/0045 , A43B3/0063 , A43B7/14 , A43B7/142 , A43B7/1425 , A43B7/1435 , A43B7/144 , A43B7/1445 , A43B7/22 , A43B7/32 , A43B13/12 , A43B13/187 , A43B17/102
摘要： Footwear comprising a sole. The sole has a heel section for supporting a heel of the foot. The heel section has medial and lateral regions. At least a portion of the lateral region has a first compressive resilience for attenuating the shock of impact to the wearer during running and walking. Further, the sole has an arch section forward of the heel section for supporting an arch of the foot. The arch section also has medial and lateral regions. At least a portion of the lateral region of the arch section has the first compressive resilience and at least a portion of the medial region of the arch section has a second compressive resilience harder than the first compressive resilience for providing firm support for the foot during running and walking. In addition, the sole has a forefoot section forward of the arch section for supporting a ball of the foot including first, second, third, fourth and fifth metatarsal heads and associated metatarsal necks, proximal phalanges and metatarsal phalangeal joints. The forefoot section has a first region for supporting the first, second, third, fourth and fifth metatarsal heads, associated phalanges and metatarsal phalangeal joints, and the metatarsal neck associated with the fifth metatarsal head and a second region for supporting at least one of the metatarsal necks associated with the second and third metatarsal heads. The first region of the forefoot section has the first compressive resilience and the second region of the forefoot section has the second compressive resilience.
摘要翻译： 鞋类包括鞋底。 鞋底具有用于支撑足部脚跟的脚跟部分。 脚跟部分具有内侧和外侧区域。 横向区域的至少一部分具有第一压缩弹性，用于在运行和行走期间减弱对穿着者的冲击冲击。 此外，鞋底具有用于支撑足弓的脚跟部分的前方的拱形部分。 拱段也有内侧和外侧的区域。 拱形部分的横向区域的至少一部分具有第一压缩弹性，并且拱形部分的内侧区域的至少一部分具有比第一压缩弹性更硬的第二压缩弹性，用于在运行期间为脚提供牢固的支撑 和走路。 此外，鞋底具有弓形部分前方的脚前区段，用于支撑足部球包括第一，第二，第三，第四和第五跖骨头和相关的跖骨颈，近端指骨和跖骨指骨关节。 前足部分具有用于支撑第一，第二，第三，第四和第五跖骨头，相关趾骨和跖骨指骨关节的第一区域，以及与第五跖骨头部相关联的跖骨颈部和用于支撑至少一个 与第二和第三跖骨头相关的跖骨颈部。 前足部分的第一区域具有第一压缩弹性并且前足部分的第二区域具有第二压缩弹性。
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37.发明授权公开(公告)号：US06175847B1
公开(公告)日：2001-01-16
申请号：US09120814
申请日：1998-07-22
IPC分类号： G06F738
CPC分类号： G06F5/012 , G06F7/49957
摘要： The present invention describes an apparatus and method that normalizes an ANSI/IEEE 754-1985 floating point arithmetic intermediate result having a fraction and exponent. The exponent is pre-incremented by one prior to normalization. During normalizaion, the most significant binary “1” of the fraction is shifted left until it resides in the carry bit. For each left shift performed, the incremented exponent is decremented once.
摘要翻译： 本发明描述了对具有分数和指数的ANSI / IEEE 754-1985浮点运算中间结果进行归一化的装置和方法。 在归一化之前，指数预先递增1。 在正常化期间，分数的最高有效二进制“1”向左移动，直到其驻留在进位中。 对于执行的每个左移，递增的指数递减一次。
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38.发明授权Division unit with normalization circuit and plural divide engines for receiving instructions when divide engine availability is indicated 有权分配单元具有归一化电路和多个除法引擎，用于在分配发动机可用性时指示公开(公告)号：US09086890B2
公开(公告)日：2015-07-21
申请号：US13345391
申请日：2012-01-06
CPC分类号： G06F9/3895 , G06F7/49936 , G06F7/535 , G06F7/5375 , G06F9/3001 , G06F9/3875 , G06F9/3885
摘要： Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit.
摘要翻译： 公开了涉及包括用于划分和/或平方根操作的硬件支持的集成电路的技术。 在一个实施例中，公开了一种集成电路，其包括分割单元，该分割单元又包括归一化电路和多个除法引擎。 归一化电路被配置为归一化一组操作数。 每个分频引擎被配置为对从归一化电路接收的相应的归一化操作数集进行操作。 在一些实施例中，集成电路包括调度器单元，其被配置为选择用于向包括该分割单元的多个执行单元发布的指令。 调度器单元还被配置为保持指示当前正在由分割单元操作的指令的数量的计数器，并且基于计数器确定是否计划用于发布到分割单元的后续指令。
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39.发明授权Apparatus and method for handling dependency conditions between floating-point instructions 有权用于处理浮点指令之间依赖条件的装置和方法公开(公告)号：US08458444B2
公开(公告)日：2013-06-04
申请号：US12428459
申请日：2009-04-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/30032 , G06F9/30109 , G06F9/384 , G06F9/3851 , G06F9/3861
摘要： Techniques for handling dependency conditions, including evil twin conditions, are disclosed herein. An instruction may designate a source register comprising two portions. The source register may be a double-precision register and its two portions may be single-precision portions, each specified as destinations by two other single-precision instructions. Execution of these two single-precision instructions, especially on a register renaming machine, may result in the appropriate values for the two portions of the source register being stored in different physical locations, which can complicate execution of an instruction stream. In response to detecting a potential dependency, one or more instructions may be inserted in an instruction stream to enable the appropriate values to be stored within one physical double precision register, eliminating an actual or potential evil twin dependency. Embodiments including a compiler that inserts instructions in a generated instruction stream to eliminate dependency conditions are also contemplated.
摘要翻译： 用于处理依赖条件的技术，包括邪恶的双重条件。 指令可以指定包括两个部分的源寄存器。 源寄存器可以是双精度寄存器，其两部分可以是单精度部分，每一部分由两个其他单精度指令指定为目标。 执行这两个单精度指令，特别是在寄存器重命名机上，可能会导致源寄存器的两个部分的适当值存储在不同的物理位置，这会使指令流的执行变得复杂。 响应于检测到潜在依赖性，可以在指令流中插入一个或多个指令，以使适当的值存储在一个物理双精度寄存器中，从而消除实际或潜在的恶性倚靠。 包括编译器的实施例也包括在生成的指令流中插入指令以消除依赖条件的编译器。
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40.发明授权Apparatus and method for implementing hardware support for denormalized operands for floating-point divide operations 有权用于实现用于浮点除法运算的非归一化操作数的硬件支持的装置和方法公开(公告)号：US08452831B2
公开(公告)日：2013-05-28
申请号：US12415370
申请日：2009-03-31
CPC分类号： G06F7/4873 , G06F7/49915 , G06F7/49936
摘要： A floating-point circuit may include a floating-point operand normalization circuit configured to receive input floating-point operands of a given floating-point divide operation, the operands comprising a dividend and a divisor, as well as a divide engine coupled to the normalization circuit. In response to determining that one or more of the input floating-point operands is a denormal number, the operand normalization circuit may be further configured to normalize the one or more of the input floating-point operands and output a normalized dividend and normalized divisor to the divide engine, and dependent upon respective numbers of leading zeros of the dividend and divisor prior to normalization, generate a value indicative of a maximum possible number of digits of a quotient (NDQ). The divide engine may be configured to iteratively generate NDQ digits of a floating-point quotient from the normalized dividend and the normalized divisor provided by the floating-point operand normalization circuit.
摘要翻译： 浮点电路可以包括浮点操作数归一化电路，其被配置为接收给定浮点除法运算的输入浮点操作数，所述操作数包括除数和除数，以及耦合到归一化的除法引擎 电路。 响应于确定一个或多个输入浮点操作数是反正态数，操作数归一化电路还可以被配置为对输入浮点操作数中的一个或多个进行归一化，并将归一化的除数和归一化除数输出到 除法引擎，并且依赖于归一化之前的除数和除数的前导零的相应数量，生成指示商（NDQ）的最大可能数位数的值。 划分引擎可以被配置为从浮动点操作数归一化电路提供的归一化除数和归一化除数迭代生成浮点商的NDQ数字。
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