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1.发明授权Processor and method for implementing instruction support for multiplication of large operands 有权用于实现大操作数乘法的指令支持的处理器和方法公开(公告)号：US08438208B2
公开(公告)日：2013-05-07
申请号：US12488372
申请日：2009-06-19
CPC分类号： G06F7/4876 , G06F2207/382
摘要： A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a hardware multiplier datapath circuit, where the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M. In response to receiving a single instance of a large-operand multiplication instruction defined within the ISA, wherein at least one of the operands of the large-operand multiplication instruction includes more than the maximum number of bits M, the instruction execution unit is configured to multiply operands of the large-operand multiplication instruction within the hardware multiplier datapath circuit to determine a result of the large-operand multiplication instruction without execution of programmer-selected instructions within the ISA other than the large-operand multiplication instruction.
摘要翻译： 包括用于实现大操作数乘法的指令支持的处理器可以从定义的指令集架构（ISA）发出用于执行编程器可选择指令的执行。 处理器可以包括指令执行单元，其包括硬件乘法器数据路径电路，其中硬件乘法器数据路径电路被配置为对具有最大位数M的操作数进行乘法。响应于接收到在其中定义的大操作数乘法指令的单个实例 所述ISA，其中所述大操作数乘法指令的操作数中的至少一个包括多于所述最大位数M，所述指令执行单元被配置为将所述大操作数乘法指令在所述硬件乘法器数据通路电路内的操作数乘以 确定大操作数乘法指令的结果，而不在大操作数乘法指令之外执行ISA内的编程器选择指令。
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2.发明申请PROCESSOR AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR MULTIPLICATION OF LARGE OPERANDS 有权用于实施大规模操作的指导性支持的处理器和方法公开(公告)号：US20100325188A1
公开(公告)日：2010-12-23
申请号：US12488372
申请日：2009-06-19
IPC分类号： G06F7/52
CPC分类号： G06F7/4876 , G06F2207/382
摘要： A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a hardware multiplier datapath circuit, where the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M. In response to receiving a single instance of a large-operand multiplication instruction defined within the ISA, wherein at least one of the operands of the large-operand multiplication instruction includes more than the maximum number of bits M, the instruction execution unit is configured to multiply operands of the large-operand multiplication instruction within the hardware multiplier datapath circuit to determine a result of the large-operand multiplication instruction without execution of programmer-selected instructions within the ISA other than the large-operand multiplication instruction.
摘要翻译： 包括用于实现大操作数乘法的指令支持的处理器可以从定义的指令集架构（ISA）发出用于执行编程器可选择指令的执行。 处理器可以包括指令执行单元，其包括硬件乘法器数据路径电路，其中硬件乘法器数据路径电路被配置为对具有最大位数M的操作数进行乘法。响应于接收到在其中定义的大操作数乘法指令的单个实例 所述ISA，其中所述大操作数乘法指令的操作数中的至少一个包括多于所述最大位数M，所述指令执行单元被配置为将所述大操作数乘法指令在所述硬件乘法器数据通路电路内的操作数乘以 确定大操作数乘法指令的结果，而不在大操作数乘法指令之外执行ISA内的编程器选择指令。
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3.发明授权Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor 有权在多线程处理器中支持不同延迟指令流水线的装置和方法公开(公告)号：US07478225B1
公开(公告)日：2009-01-13
申请号：US10881071
申请日：2004-06-30
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3873
摘要： An apparatus and method to support pipelining of variable-latency instructions in a multithreaded processor. In one embodiment, a processor may include instruction fetch logic configured to issue a first and a second instruction from different ones of a plurality of threads during successive cycles. The processor may also include first and second execution units respectively configured to execute shorter-latency and longer-latency instructions and to respectively write shorter-latency or longer-latency instruction results to a result write port during a first or second writeback stage. The first writeback stage may occur a fewer number of cycles after instruction issue than the second writeback stage. The instruction fetch logic may be further configured to guarantee result write port access by the second execution unit during the second writeback stage by preventing the shorter-latency instruction from issuing during a cycle for which the first writeback stage collides with the second writeback stage.
摘要翻译： 支持多线程处理器中可变延迟指令流水线的装置和方法。 在一个实施例中，处理器可以包括指令提取逻辑，其被配置为在连续循环期间从多个线程中的不同线程发出第一和第二指令。 处理器还可以包括第一和第二执行单元，其分别被配置为执行较短延迟和较长延迟的指令，并且在第一或第二回写阶段期间分别将较短等待时间或更长延迟的指令结果写入结果写入端口。 指令发布后的第一个回写阶段可能发生的次数比第二个回写阶段少。 指令提取逻辑可以被进一步配置为通过在第一写回阶段与第二回写阶段相冲突的周期期间防止短暂延迟指令发出来保证第二执行单元在第二写回阶段期间的结果写入端口访问。
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4.发明授权Processor and method for implementing instruction support for hash algorithms 有权用于实现散列算法的指令支持的处理器和方法公开(公告)号：US08832464B2
公开(公告)日：2014-09-09
申请号：US12415403
申请日：2009-03-31
IPC分类号： G06F12/14 , H04L9/32 , H04L9/00 , G06F9/30 , G06F21/76 , H04L9/12 , H04L9/18 , H04L9/06 , G06F9/38
CPC分类号： G06F12/1408 , G06F9/30007 , G06F9/3802 , G06F9/3836 , G06F9/3851 , G06F9/3895 , G06F21/76 , H04L9/0643 , H04L9/12 , H04L9/18 , H04L2209/125
摘要： A processor including instruction support for implementing hash algorithms may issue, for execution, programmer-selectable hash instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include hash instructions defined within the ISA. In addition, the hash instructions may be executable by the cryptographic unit to implement a hash that is compliant with one or more respective hash algorithm specifications. In response to receiving a particular hash instruction defined within the ISA, the cryptographic unit may retrieve a set of input data blocks from a predetermined set of architectural registers of the processor, and generate a hash value of the set of input data blocks according to a hash algorithm that corresponds to the particular hash instruction.
摘要翻译： 包括用于实现散列算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发布执行编程器可选择的散列指令。 处理器可以包括可以接收执行指令的密码单元。 这些指令包括ISA内定义的散列指令。 此外，哈希指令可以由密码单元执行，以实现符合一个或多个相应散列算法规范的散列。 响应于接收在ISA内定义的特定散列指令，加密单元可以从处理器的预定的体系结构寄存器集中检索一组输入数据块，并且根据一个输入数据块生成一组输入数据块的哈希值 哈希算法对应于特定的哈希指令。
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公开(公告)号：US08195919B1
公开(公告)日：2012-06-05
申请号：US11927177
申请日：2007-10-29
IPC分类号： G06F13/00
CPC分类号： G06F12/0842 , G06F9/3001 , G06F9/30043 , G06F9/3824 , G06F12/0855
摘要： Determining an effective address of a memory with a three-operand add operation in single execution cycle of a multithreaded processor that can access both segmented memory and non-segmented memory. During that cycle, the processor determines whether a memory segment base is zero. If the segment base is zero, the processor can access a memory location at the effective address without adding the segment base. If the segment base is not zero, such as when executing legacy code, the processor consumes another cycle to add the segment base to the effective address. Similarly, the processor consumes another cycle if the effective address or the linear address is misaligned. An integer execution unit that performs the three-operand add using a carry-save adder coupled to a carry look-ahead adder. If the segment base is not zero, the effective address is fed back through the integer execution unit to add the segment base.
摘要翻译： 在可以访问分段存储器和非分段存储器的多线程处理器的单个执行周期中确定具有三操作数添加操作的存储器的有效地址。 在该周期期间，处理器确定存储器段基数是否为零。 如果分段基数为零，则处理器可以在有效地址的情况下访问存储器位置，而不添加分段基。 如果段基数不为零，例如执行遗留代码时，处理器消耗另一个周期，将段基数添加到有效地址。 类似地，如果有效地址或线性地址不对齐，则处理器消耗另一个周期。 整数执行单元，其使用耦合到进位先行加法器的进位保存加法器来执行三运算加法。 如果段基数不为零，则通过整数执行单元反馈有效地址以添加段基。
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6.发明申请PROCESSOR AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR HASH ALGORITHMS 有权用于执行哈希算法的指令支持的处理器和方法公开(公告)号：US20100250966A1
公开(公告)日：2010-09-30
申请号：US12415403
申请日：2009-03-31
CPC分类号： G06F12/1408 , G06F9/30007 , G06F9/3802 , G06F9/3836 , G06F9/3851 , G06F9/3895 , G06F21/76 , H04L9/0643 , H04L9/12 , H04L9/18 , H04L2209/125
摘要： A processor including instruction support for implementing hash algorithms may issue, for execution, programmer-selectable hash instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include hash instructions defined within the ISA. In addition, the hash instructions may be executable by the cryptographic unit to implement a hash that is compliant with one or more respective hash algorithm specifications. In response to receiving a particular hash instruction defined within the ISA, the cryptographic unit may retrieve a set of input data blocks from a predetermined set of architectural registers of the processor, and generate a hash value of the set of input data blocks according to a hash algorithm that corresponds to the particular hash instruction.
摘要翻译： 包括用于实现散列算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发布执行编程器可选择的散列指令。 处理器可以包括可以接收执行指令的密码单元。 这些指令包括ISA内定义的散列指令。 此外，哈希指令可以由密码单元执行，以实现符合一个或多个相应散列算法规范的散列。 响应于接收在ISA内定义的特定散列指令，加密单元可以从处理器的预定的体系结构寄存器集中检索一组输入数据块，并且根据一个输入数据块生成一组输入数据块的哈希值 哈希算法对应于特定的哈希指令。
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7.发明授权Register window management using first pipeline to change current window and second pipeline to read operand from old window and write operand to new window 有权注册窗口管理使用第一个流水线更改当前窗口，第二个管道从旧窗口读取操作数，并将操作数写入新窗口公开(公告)号：US07216216B1
公开(公告)日：2007-05-08
申请号：US10881556
申请日：2004-06-30
CPC分类号： G06F9/30127 , G06F9/30043 , G06F9/3012 , G06F9/3867 , G06F9/3885
摘要： In one embodiment, a processor is configured to execute a window swap instruction. The processor comprises a register file (that comprises a plurality of registers) and first and second execution units coupled to the register file. A first pipeline associated with the first execution unit has a first number of pipeline stages, and a second pipeline associated with the second execution unit has a second number of pipeline stages. The first execution unit is configured to change the current register window from the first register window to the second register window in the register file in response to the instruction. The second execution unit is configured to perform an operation defined by the instruction and write the result to the register file. The second number of pipeline stages exceeds the first number, whereby the second register window is established in the register file prior to writing the result.
摘要翻译： 在一个实施例中，处理器被配置为执行窗口交换指令。 处理器包括寄存器文件（包括多个寄存器）以及耦合到寄存器文件的第一和第二执行单元。 与第一执行单元相关联的第一流水线具有第一数量的流水线级，并且与第二执行单元相关联的第二流水线具有第二数量的流水线级。 第一执行单元被配置为响应于指令将当前寄存器窗口从第一寄存器窗口改变到寄存器堆中的第二寄存器窗口。 第二执行单元被配置为执行由指令定义的操作，并将结果写入寄存器文件。 第二数量的流水线级超过第一个数字，从而在写入结果之前在寄存器文件中建立第二个寄存器窗口。
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8.发明授权Method for selecting between divide instructions associated with respective threads in a multi-threaded processor 有权用于在多线程处理器中与相应线程相关联的除法指令之间进行选择的方法公开(公告)号：US07941642B1
公开(公告)日：2011-05-10
申请号：US10881216
申请日：2004-06-30
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/3851
摘要： In one embodiment, a multithreaded processor includes a multithreaded instruction source that may provide a plurality of instructions each corresponding to a respective one of a plurality of threads. The multithreaded processor also includes a pick unit coupled to the multithreaded instruction source. The pick unit may select in a given cycle, a first divide instruction corresponding to one thread of the plurality of threads and a second divide instruction corresponding to another thread of the plurality of threads based upon a thread selection algorithm. Further, the multithreaded processor includes a storage coupled to a functional unit including a divider configured to execute the first divide instruction and the second divide instruction. The storage may store one of the first and the second divide instructions during execution of the other of the first and the second divide instructions.
摘要翻译： 在一个实施例中，多线程处理器包括多线程指令源，其可以提供多个指令，每个指令对应于多个线程中的相应一个线程。 多线程处理器还包括耦合到多线程指令源的拾取单元。 拾取单元可以在给定周期中选择对应于多个线程中的一个线程的第一除法指令和基于线程选择算法对应于多个线程中的另一线程的第二除法指令。 此外，多线程处理器包括耦合到功能单元的存储器，该功能单元包括被配置为执行第一除法指令和第二除法指令的分配器。 存储器可以在执行第一和第二除法指令中的另一个指令期间存储第一和第二除法指令之一。
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公开(公告)号：US07523330B2
公开(公告)日：2009-04-21
申请号：US10881246
申请日：2004-06-30
IPC分类号： G06F1/26
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G06F9/3851 , Y02D10/128 , Y02D10/171
摘要： A method and apparatus for controlling power consumption in a multi-threaded processor. In one embodiment, the processor includes at least one logic unit for processing instructions. The logic unit includes a plurality of positions, wherein each of the plurality of positions corresponds to at least one instruction thread. Clock signals may be provided to the logic unit via a clock gating unit. The clock gating unit is configured to inhibit a clock signal from being provided to a corresponding one of the thread positions when no instruction thread is active for that position. The inhibiting of the clock signal for an inactive thread position may reduce power consumption by the processor.
摘要翻译： 一种用于控制多线程处理器中的功耗的方法和装置。 在一个实施例中，处理器包括用于处理指令的至少一个逻辑单元。 逻辑单元包括多个位置，其中多个位置中的每一个对应于至少一个指令线程。 时钟信号可以经由时钟门控单元提供给逻辑单元。 时钟门控单元被配置为当没有指令线程对于该位置有效时，禁止将时钟信号提供给相应的一个线程位置。 禁止线程位置的时钟信号的抑制可能会降低处理器的功耗。
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公开(公告)号：US08458446B2
公开(公告)日：2013-06-04
申请号：US12570682
申请日：2009-09-30
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30123 , G06F9/30127 , G06F9/3013 , G06F9/30141 , G06F9/3851 , G11C8/16
摘要： A processor includes an instruction fetch unit configured to issue instructions for execution, where the instructions are selected from a number of threads, where each given instruction has a corresponding thread identifier, and where at least some of the instructions specify operand(s) via register identifiers. A register file stores operands usable by the instructions, and may include several banks, each corresponding to a register identifiers and including several entries corresponding to the several threads, wherein the entries are configured to store data values. In response to receiving a request to read a particular register identifier for a given thread identifier, the register file may be configured to decode the given thread identifier to retrieve entries from the banks that correspond to the given thread identifier. The register file may further select, from among the retrieved entries, a data value corresponding to the particular register identifier to be output.
摘要翻译： 处理器包括：指令获取单元，被配置为发出用于执行的指令，其中从多个线程中选择指令，其中每个给定指令具有对应的线程标识符，并且其中至少一些指令经由寄存器指定操作数 身份标识。 寄存器文件存储指令可用的操作数，并且可以包括几个存储体，每个存储体对应于寄存器标识符，并且包括与多个线程对应的多个条目，其中条目被配置为存储数据值。 响应于接收到针对给定线程标识符读取特定寄存器标识符的请求，寄存器文件可以被配置为对给定的线程标识符进行解码以从对应于给定线程标识符的存储体检索条目。 寄存器文件还可以从检索到的条目中选择与要输出的特定寄存器标识符对应的数据值。
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