公开(公告)号：US07349266B2

公开(公告)日：2008-03-25

申请号：US10865274

申请日：2004-06-10

申请人： Ravindraraj Ramaraju ,  George P. Hoekstra ,  Prashant U. Kenkare

发明人： Ravindraraj Ramaraju ,  George P. Hoekstra ,  Prashant U. Kenkare

IPC分类号： G11C7/10

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/16

摘要： A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells. Each latch circuit has an input coupled to a data line and a first output and a second output to provide complementary latched values dependent upon a value of the data line. For each latch of the plurality of latches, the first output is coupled to a first bit line of a pair of the plurality such that a value of the first bit line is continuously determined by the first output during memory device operation and the second output is coupled to a second bit line of the pair such that a value of the second bit line is continuously determined by the second output during memory device operation.

摘要翻译： 存储器件包括多对互补位线和多个锁存电路。 多对互补位线对中的每一对耦合到一列存储单元。 每个锁存电路具有耦合到数据线和第一输出和第二输出的输入，以提供取决于数据线的值的互补锁存值。 对于多个锁存器中的每个锁存器，第一输出耦合到一对多对的第一位线，使得在存储器件操作期间第一位线的值被第一输出连续地确定，并且第二输出是 耦合到该对的第二位线，使得在存储器件操作期间第二位线的值由第二输出连续地确定。

公开(公告)号：US07185170B2

公开(公告)日：2007-02-27

申请号：US10928399

申请日：2004-08-27

申请人： Ravindraraj Ramaraju ,  David P. Burgess ,  Troy L. Cooper ,  Eric V. Fiene ,  George P. Hoekstra

发明人： Ravindraraj Ramaraju ,  David P. Burgess ,  Troy L. Cooper ,  Eric V. Fiene ,  George P. Hoekstra

IPC分类号： G06F12/00 ,  G06F9/26 ,  G06F9/34

CPC分类号： G06F12/126 ,  G06F12/1027

摘要： A system (10) translates memory addresses. Processing circuitry (12) provides an effective address to a storage array (14, 16) having a plurality of stored effective addresses, each of the plurality of stored effective addresses having a corresponding pair of a lock bit and a valid bit. An output tag value and a single valid bit are provided to a comparator (18). The lock bit defines one of two predetermined classes of tasks executed by the system. The single valid bit is applicable to both of the two predetermined classes of tasks. The lock bit qualifies the clearing of the single valid bit. The comparator respectively compares the output tag value and the single valid bit with a predetermined effective address and a predetermined bit value. An output hit signal is provided when a match occurs to validate a physical address provided by a physical address array (20).

摘要翻译： 系统（10）翻译存储器地址。 处理电路（12）向具有多个存储的有效地址的存储阵列（14,16）提供有效地址，所述多个存储的有效地址中的每一个具有相应的一对锁定位和有效位。 将输出标签值和单个有效位提供给比较器（18）。 锁定位定义系统执行的两个预定任务类别之一。 单个有效位适用于两个预定类别的任务。 锁定位限定单个有效位的清除。 比较器分别将输出标签值和单个有效位与预定的有效地址和预定位值进行比较。 当发生匹配以验证由物理地址阵列（20）提供的物理地址时，提供输出命中信号。

公开(公告)号：US4866676A

公开(公告)日：1989-09-12

申请号：US172514

申请日：1988-03-24

申请人： Richard D. Crisp ,  George P. Hoekstra ,  George G. Watkins

发明人： Richard D. Crisp ,  George P. Hoekstra ,  George G. Watkins

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  G11C29/36

CPC分类号： G11C29/78 ,  G11C29/24 ,  G11C29/36

摘要： A read/write memory has bit line pairs variously having a first or a second true/complement orientation. Data is selectively coupled to and from the bit line pairs to and from a data line pair via a column decoder. The memory has redundant bit line pairs aligned in the first true/complement arrangement. When a redundant bit line pair is implemented, the logic state of the data is inverted both for reading and for writing if the replaced bit line pair is of the second true/complement orientation. This results in the voltage impressed onto the memory cell for a given logic state is the same for the redundant bit line pair as for the bit line pair that it replaced.