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公开(公告)号：US20100295638A1
公开(公告)日：2010-11-25
申请号：US12852743
申请日：2010-08-09
CPC分类号： H02M3/34
摘要： A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators.
摘要翻译： MEMS磁通开关被制造为铁磁芯。 芯包括中心悬臂，其被制造为可以以其机械和材料性质确定的共振频率振荡的自由梁。 中心悬臂由相关运动振荡器施加的脉冲移动，运动振荡器可以是磁性或电动执行器。
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32.发明授权Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits 有权用于在半导体集成电路上制造高价值电感器的晶片级的装置和方法公开(公告)号：US07829425B1
公开(公告)日：2010-11-09
申请号：US11504972
申请日：2006-08-15
申请人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Andrei Papou
IPC分类号： H01L21/20
CPC分类号： H01L23/5227 , C23C28/023 , C25D5/022 , C25D7/123 , C25D17/001 , H01L27/0207 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.
摘要翻译： 用于直接在半导体集成电路之上晶圆级制造高值电感器的装置和方法。 该装置和方法包括制造包括多个骰子的半导体晶片，每个骰子包括电源电路和开关节点。 一旦制造晶片，则分别将多个电感器直接制造在晶片上的多个晶片上。 每个电感器通过在形成在晶片上的互连电介质层上形成多个磁芯电感器构件来制造。 然后在每个管芯上方的多个磁芯电感器部件上形成绝缘层，然后形成电感器线圈。 分别在多个电感器上形成电镀磁性层，以提高结构的磁导率和电感。
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33.发明授权Method of forming a saucer-shaped half-loop MEMS inductor with very low resistance 有权形成具有非常低电阻的碟形半环MEMS电感器的方法公开(公告)号：US07676922B1
公开(公告)日：2010-03-16
申请号：US11820464
申请日：2007-06-19
IPC分类号： H01K3/10
CPC分类号： H01F17/0033 , H01F41/046 , H01L23/5227 , H01L2924/0002 , Y10T29/4902 , Y10T29/49069 , Y10T29/49165 , H01L2924/00
摘要： A micro-electromechanical system (MEMS) inductor is formed in a saucer shape that completely surrounds a magnetic core structure which is formed from a ferromagnetic material. In addition, an array of MEMS inductors can be formed by dividing up the saucer-shaped MEMS inductor into a number of electrically-isolated MEMS inductor wedges.
摘要翻译： 微机电系统（MEMS）电感器形成为完全围绕由铁磁材料形成的磁芯结构的碟形形状。 此外，可以通过将碟形MEMS电感器分成多个电隔离的MEMS电感器楔形物来形成MEMS电感器阵列。
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34.发明授权Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits 有权用于在半导体集成电路上制造高价值电感器的晶片级的装置和方法公开(公告)号：US07652348B1
公开(公告)日：2010-01-26
申请号：US11495143
申请日：2006-07-27
申请人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Andrei Papou
IPC分类号： H01L21/20
CPC分类号： H01L23/645 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/19015 , H01L2924/19104 , H01L2924/00
摘要： An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer and are in electrical contact with a switching node of the power circuitry on each die respectively. The inductors are fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer for each die on the wafer. An insulating layer and then inductor coils are then formed over the plurality of magnetic core inductor members over each die. A layer of magnetic paste is also optionally provided over each inductor coil to further increase inductance.
摘要翻译： 用于直接在半导体集成电路之上晶圆级制造高值电感器的装置和方法。 该装置和方法包括制造包括多个骰子的半导体晶片，每个骰子包括电源电路。 一旦制造晶片，则将多个电感器直接制造在晶片上的多个晶片上，并分别与每个晶片上的电源电路的开关节点电接触。 通过在晶片上的每个管芯的互连电介质层上形成多个磁芯电感器构件来制造电感器。 然后在每个管芯上的多个磁芯电感器部件上形成绝缘层，然后形成电感线圈。 也可以在每个电感线圈上设置一层磁性浆料，以进一步增加电感。
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35.发明授权Method of forming a metal trace with reduced RF impedance resulting from the skin effect 有权形成由皮肤效应引起的具有降低的RF阻抗的金属迹线的方法公开(公告)号：US07309639B1
公开(公告)日：2007-12-18
申请号：US10820476
申请日：2004-04-08
申请人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Michael Mian , Robert Drury
发明人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Michael Mian , Robert Drury
IPC分类号： H01L21/20
CPC分类号： H01L23/5227 , H01L23/5283 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.
摘要翻译： 以千兆赫兹频率的金属迹线的RF阻抗通过形成金属迹线而减小，以具有从基极区域延伸的基极区域和多个指状物。 当形成为具有多个环时，金属迹线形成具有增加的Q的电感器。
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公开(公告)号：US07268410B1
公开(公告)日：2007-09-11
申请号：US11041658
申请日：2005-01-24
申请人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Robert Drury
发明人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Robert Drury
IPC分类号： H01L29/00
CPC分类号： H02M7/003
摘要： Improvements in the level of integration of a core buck and/or boost DC-DC voltage regulator sub-circuit lead to a lower manufacturing cost structure, an improved performance from lessened intrinsic parasitic resistance, a smaller die size and, thus, higher wafer yield. Further, by integrating certain components on-chip, the cost and complexity of the conventional hybrid circuit implementation is improved.
摘要翻译： 核心降压和/或升压DC-DC电压调节器子电路的集成度的改进导致较低的制造成本结构，通过减小的内在寄生电阻改善的性能，更小的管芯尺寸以及因此更高的晶片产量 。 此外，通过集成片上的某些部件，提高了传统混合电路实现的成本和复杂性。
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公开(公告)号：US07157891B1
公开(公告)日：2007-01-02
申请号：US11057967
申请日：2005-02-15
申请人： Rob Drury , Peter J. Hopper , Kyuwoon Hwang , Peter Johnson
发明人： Rob Drury , Peter J. Hopper , Kyuwoon Hwang , Peter Johnson
IPC分类号： G05F1/44
CPC分类号： H02M3/1584 , H02M2003/1586
摘要： An integrated DC—DC converter circuit in which multiple switched circuits operate in parallel to drive the output electrode with multiple pulsed charging voltages such that the corresponding respective output ripple voltage components combine with destructive interference, thereby reducing the net output ripple voltage.
摘要翻译： 一种集成的DC-DC转换器电路，其中多个开关电路并联操作以驱动具有多个脉冲充电电压的输出电极，使得相应的相应的输出纹波电压分量与破坏性干扰相结合，从而降低净输出纹波电压。
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38.发明授权Method of etching a lateral trench under a drain junction of a MOS transistor 有权蚀刻在MOS晶体管的漏极结下方的横向沟槽的方法公开(公告)号：US07023068B1
公开(公告)日：2006-04-04
申请号：US10716277
申请日：2003-11-17
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/30608 , H01L21/3083 , H01L21/3086 , H01L21/76232 , H01L21/76264 , H01L29/78
摘要： In a MOS transistor, the drain capacitance is reduced by forming a lateral trench underneath the drain. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer.
摘要翻译： 在MOS晶体管中，通过在漏极下方形成横向沟槽来减小漏极电容。 这通常通过使用<100>取向晶片的<110>方向的各向异性湿蚀刻工艺来完成。
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39.发明授权公开(公告)号：US06853079B1
公开(公告)日：2005-02-08
申请号：US10219235
申请日：2002-08-15
申请人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Michael Mian , Robert Drury
发明人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Michael Mian , Robert Drury
IPC分类号： H01L23/522 , H01L23/48
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The radio frequency (RF) impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fins that extend away from the base region. When formed in a spiral configuration having a number of loops, the metal trace forms an inductor with an increased quality factor (Q).
摘要翻译： 以千兆赫兹频率的金属迹线的射频（RF）阻抗通过形成金属迹线而减小，以具有从基极区域延伸的基极区域和多个鳍片。 当以具有多个环的螺旋构造形成时，金属迹线形成具有增加的品质因数（Q）的电感器。
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40.发明授权Dual damascene metal trace with reduced RF impedance resulting from the skin effect 失效双镶嵌金属痕迹，由皮肤效应引起的RF阻抗降低公开(公告)号：US06703710B1
公开(公告)日：2004-03-09
申请号：US10219791
申请日：2002-08-15
申请人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Michael Mian , Robert Drury
发明人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Michael Mian , Robert Drury
IPC分类号： H01L2348
CPC分类号： H01L23/5227 , H01L21/76802 , H01L21/76838 , H01L23/5283 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.
摘要翻译： 以千兆赫兹频率的金属迹线的RF阻抗通过形成金属迹线而减小，以具有从基极区域延伸的基极区域和多个指状物。 当形成为具有多个环时，金属迹线形成具有增加的Q的电感器。
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