公开(公告)号：US20060208321A1

公开(公告)日：2006-09-21

申请号：US11306663

申请日：2006-01-05

申请人： Darin Chan ,  Simon Chan ,  Paul King

发明人： Darin Chan ,  Simon Chan ,  Paul King

IPC分类号： H01L29/94 ,  H01L23/48

CPC分类号： H01L27/112 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a suicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

摘要翻译： 集成电路设置有半导体衬底，当半导体衬底反应以形成这种硅化物时，半导体衬底被掺杂有一定类型的可氧化掺杂剂的分离类型的硅化物顶部表面的浓度。 栅极电介质位于半导体衬底上，栅极位于栅极电介质上。 源极/漏极结在半导体衬底中。 硅化物在源极/漏极结上，掺杂剂分离到硅化物的顶表面。 分离的掺杂剂的顶表面上的掺杂剂被氧化以在硅化物之上形成氧化掺杂剂的绝缘层。 层间电介质在半导体衬底之上。 触点和连接点位于硅化物之上的氧化掺杂剂的绝缘层的层间电介质中。

公开(公告)号：US20060197154A1

公开(公告)日：2006-09-07

申请号：US11071375

申请日：2005-03-03

申请人： Mario Pelella ,  Darin Chan ,  Simon Chan

发明人： Mario Pelella ,  Darin Chan ,  Simon Chan

IPC分类号： H01L27/12

CPC分类号： H01L21/823481 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor component having analog and logic circuit elements manufactured from an SOI substrate and a method for manufacturing the semiconductor component. An SOI substrate has a support wafer coupled to an active wafer through an insulating material. Openings are formed in the active wafer, extend through the insulating material, and expose portions of the support wafer. Epitaxial semiconductor material is grown on the exposed portions of the support wafer. Analog circuitry is manufactured from the epitaxially grown semiconductor material and high performance logic circuitry is manufactured from the active wafer. The processing steps for manufacturing the analog circuitry are decoupled from the steps for manufacturing the high performance logic circuitry. A substrate contact is made from a portion of the epitaxially grown semiconductor material that is electrically isolated from the portion in which the analog circuitry is manufactured.

摘要翻译： 具有由SOI衬底制造的模拟和逻辑电路元件的半导体元件和用于制造半导体元件的方法。 SOI衬底具有通过绝缘材料耦合到有源晶片的支撑晶片。 开口形成在有源晶片中，延伸穿过绝缘材料，并暴露支撑晶片的部分。 外延半导体材料在支撑晶片的暴露部分上生长。 模拟电路由外延生长的半导体材料制成，高性能逻辑电路由有源晶片制造。 用于制造模拟电路的处理步骤与用于制造高性能逻辑电路的步骤分离。 从与制造模拟电路的部分电隔离的外延生长的半导体材料的一部分制成衬底接触。

公开(公告)号：US06232663B1

公开(公告)日：2001-05-15

申请号：US08904630

申请日：1997-08-01

申请人： Toshio Taniguchi ,  Kenji Nukui ,  Ibrahim Burki ,  Richard Huang ,  Simon Chan ,  Kazunori Imaoka ,  Kazutoshi Mochizuki

发明人： Toshio Taniguchi ,  Kenji Nukui ,  Ibrahim Burki ,  Richard Huang ,  Simon Chan ,  Kazunori Imaoka ,  Kazutoshi Mochizuki

IPC分类号： H01L2348

CPC分类号： H01L23/5329 ,  H01L21/76801 ,  H01L21/76804 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of fabricating thereof, including an insulator layer having alternately layered insulator films and boundary layers, wherein the boundary layers are more dense than the insulator films to prevent expansion and elongation of string-like defects across the boundary layers. The method includes mixing a nitrogen containing gas and a silane group gas to form an insulator film; temporarily stopping a flow of the silane group gas for approximately one to fifteen seconds to form a boundary layer over the insulator film; restarting the flow of the silane group gas; and repeating the steps of temporarily stopping and restarting for a predetermined number of times to form the plurality of alternately layered insulator films and boundary layers. The plurality of alternately layered insulator films and boundary layers is also etched at an etching rate for the insulator films greater than an etching rate for the boundary layers to form a step-shaped sloped opening.

摘要翻译： 一种半导体器件及其制造方法，包括具有交替层叠的绝缘体膜和边界层的绝缘体层，其中边界层比绝缘膜更致密，以防止跨越边界层的线状缺陷的膨胀和伸长。 该方法包括混合含氮气体和硅烷基气体以形成绝缘膜; 暂时停止硅烷气体流动约1至15秒，以在绝缘膜上形成边界层; 重新开始硅烷气体的流动; 并重复暂时停止并重新启动预定次数的步骤，以形成多个交替层叠的绝缘体膜和边界层。 多个交替层叠的绝缘体膜和边界层也以对于绝缘体膜的蚀刻速率蚀刻大于边界层的蚀刻速率以形成阶梯形倾斜开口。

公开(公告)号：US5994778A

公开(公告)日：1999-11-30

申请号：US157240

申请日：1998-09-18

申请人： Richard J. Huang ,  Guarionex Morales ,  Simon Chan

发明人： Richard J. Huang ,  Guarionex Morales ,  Simon Chan

IPC分类号： H01L21/316 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L21/02131 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/31629 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S257/915

摘要： A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

摘要翻译： 一种在制造半导体产品的方法中使用低选择性SiOF的方法，包括以下步骤：获得SiOF层; 并从SiOF层的表面上消耗氟。 在优选的实施方案中，耗尽步骤包括用含有氢的等离子体处理SiOF层的表面的步骤。 进一步优选的是，处理过的表面被钝化。 本发明还包括一种半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF半导体层包括其一个边缘处的第一区域，该第一区域耗尽氟 到预定深度。