公开(公告)号：US5994778A

公开(公告)日：1999-11-30

申请号：US157240

申请日：1998-09-18

申请人： Richard J. Huang ,  Guarionex Morales ,  Simon Chan

发明人： Richard J. Huang ,  Guarionex Morales ,  Simon Chan

IPC分类号： H01L21/316 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L21/02131 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/31629 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S257/915

摘要： A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

摘要翻译： 一种在制造半导体产品的方法中使用低选择性SiOF的方法，包括以下步骤：获得SiOF层; 并从SiOF层的表面上消耗氟。 在优选的实施方案中，耗尽步骤包括用含有氢的等离子体处理SiOF层的表面的步骤。 进一步优选的是，处理过的表面被钝化。 本发明还包括一种半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF半导体层包括其一个边缘处的第一区域，该第一区域耗尽氟 到预定深度。

公开(公告)号：US06335273B2

公开(公告)日：2002-01-01

申请号：US09443376

申请日：1999-11-19

申请人： Richard J. Huang ,  Guarionex Morales ,  Simon Chan

发明人： Richard J. Huang ,  Guarionex Morales ,  Simon Chan

IPC分类号： H01L214763

CPC分类号： H01L21/02131 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/31629 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

摘要： A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

摘要翻译： 一种在制造半导体产品的方法中使用低选择性SiOF的方法，包括以下步骤：获得SiOF层; 并从SiOF层的表面上消耗氟。 在优选的实施方案中，耗尽步骤包括用含有氢的等离子体处理SiOF层的表面的步骤。 进一步优选的是，处理过的表面被钝化。 本发明还包括一种半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF半导体层包括其一个边缘处的第一区域，该第一区域耗尽氟 到预定深度。

公开(公告)号：US08381613B2

公开(公告)日：2013-02-26

申请号：US12832636

申请日：2010-07-08

申请人： Peter Revelis ,  Simon Chan ,  Mark Van Ryswyck

发明人： Peter Revelis ,  Simon Chan ,  Mark Van Ryswyck

IPC分类号： G05G1/04

CPC分类号： F16C1/14 ,  F16C2361/45 ,  Y10T74/20438 ,  Y10T74/20612

摘要： A self-adjusting parking brake actuator includes a brake lever that is movable between brake-released and brake-applied positions. In addition, the parking brake cable adjust system includes a self-adjustment assembly having a frame; a rack mounted for movement relative to the frame along a longitudinal direction of the rack in a tension direction and an opposite direction; a cable connector for operatively connecting the rack to a brake cable, a first resilient member biasing the rack relative to the frame along its longitudinal direction in the tensioning direction, a primary locking device configured to engage the rack and permit movement of the rack relative to the frame in the tensioning direction only; a secondary locking device moveable between (a) a locking to lock the primary locking device to prevent adjusting movement of the rack relative to the frame in the tensioning direction, and (b) a releasing position to permit the primary locking device to allow adjusting movement of the rack relative to the frame in the tensioning direction by the biasing of the resilient member; and a second resilient member biasing the secondary locking device to the locking position.

摘要翻译： 自调节驻车制动器致动器包括可在制动释放和制动施加位置之间移动的制动杆。 另外，驻车制动器电缆调节系统包括具有框架的自调节组件; 安装用于沿张紧方向和相反方向沿着所述齿条的纵向方向相对于所述框架移动的齿条; 电缆连接器，用于将机架可操作地连接到制动电缆;第一弹性构件，其沿着拉伸方向上的纵向方向相对于框架偏置框架;主锁定装置，构造成接合机架并允许机架相对于 框架仅在张紧方向; 辅助锁定装置可以在（a）锁定以锁定主锁定装置之间移动以防止在张紧方向上调节齿条相对于框架的运动，以及（b）释放位置以允许主锁定装置允许调节运动 通过弹性构件的偏置而相对于框架在张紧方向上的支架; 以及将所述辅助锁定装置偏置到所述锁定位置的第二弹性构件。

公开(公告)号：US20120006143A1

公开(公告)日：2012-01-12

申请号：US12832636

申请日：2010-07-08

申请人： Peter REVELIS ,  Simon Chan ,  Mark Van Ryswyck

发明人： Peter REVELIS ,  Simon Chan ,  Mark Van Ryswyck

IPC分类号： F16C1/12

CPC分类号： F16C1/14 ,  F16C2361/45 ,  Y10T74/20438 ,  Y10T74/20612

摘要： A self-adjusting parking brake actuator includes a brake lever that is movable between brake-released and brake-applied positions. In addition, the parking brake cable adjust system includes a self-adjustment assembly having a frame; a rack mounted for movement relative to the frame along a longitudinal direction of the rack in a tension direction and an opposite direction; a cable connector for operatively connecting the rack to a brake cable, a first resilient member biasing the rack relative to the frame along its longitudinal direction in the tensioning direction, a primary locking device configured to engage the rack and permit movement of the rack relative to the frame in the tensioning direction only; a secondary locking device moveable between (a) a locking to lock the primary locking device to prevent adjusting movement of the rack relative to the frame in the tensioning direction, and (b) a releasing position to permit the primary locking device to allow adjusting movement of the rack relative to the frame in the tensioning direction by the biasing of the resilient member; and a second resilient member biasing the secondary locking device to the locking position.

摘要翻译： 自调节驻车制动器致动器包括可在制动释放和制动施加位置之间移动的制动杆。 另外，驻车制动器电缆调节系统包括具有框架的自调节组件; 安装用于沿张紧方向和相反方向沿着所述齿条的纵向方向相对于所述框架移动的齿条; 电缆连接器，用于将机架可操作地连接到制动电缆;第一弹性构件，其沿着拉伸方向上的纵向方向相对于框架偏置框架;主锁定装置，构造成接合机架并允许机架相对于 框架仅在张紧方向; 辅助锁定装置可以在（a）锁定以锁定主锁定装置之间移动以防止在张紧方向上调节齿条相对于框架的运动，以及（b）释放位置以允许主锁定装置允许调节运动 通过弹性构件的偏置而相对于框架在张紧方向上的支架; 以及将所述辅助锁定装置偏置到所述锁定位置的第二弹性构件。

公开(公告)号：US20050124170A1

公开(公告)日：2005-06-09

申请号：US10729479

申请日：2003-12-05

申请人： Mario Pelella ,  Simon Chan

发明人： Mario Pelella ,  Simon Chan

IPC分类号： C30B25/18 ,  H01L21/20 ,  H01L21/304 ,  H01L21/762 ,  H01L21/31

CPC分类号： H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3043 ,  H01L29/7842

摘要： A method of manufacturing an integrated circuit (IC) can utilizes semiconductor substrate configured in accordance with a trench process. The substrate utilizes trenches in a base layer to induce stress in a layer. The substrate can include silicon. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.

摘要翻译： 集成电路（IC）的制造方法可以利用根据沟槽工艺配置的半导体衬底。 衬底利用基层中的沟槽以在层中引起应力。 衬底可以包括硅。 沟槽在绝缘体上半导体（SOI）晶片的体基板或基底层的背侧上限定支柱。

公开(公告)号：US6043153A

公开(公告)日：2000-03-28

申请号：US937915

申请日：1997-09-25

申请人： Takeshi Nogami ,  Simon Chan

发明人： Takeshi Nogami ,  Simon Chan

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76841

摘要： A system and method for providing copper interconnect in a trench formed in a dielectric is disclosed. In one aspect, the method and system include providing a copper layer; removing a portion of the copper layer outside of the trench; annealing the copper layer; and providing a layer disposed above the copper layer. In another aspect, the method and system include providing a copper interconnect formed in a trench on a dielectric. The copper interconnect includes a copper layer disposed in the trench and a layer disposed above the copper layer. The copper layer has a bamboo structure at least one grain. The at least one grain has substantially one orientation.

摘要翻译： 公开了一种用于在形成在电介质中的沟槽中提供铜互连的系统和方法。 一方面，所述方法和系统包括提供铜层; 去除所述沟槽外部的所述铜层的一部分; 退火铜层; 并提供设置在铜层之上的层。 在另一方面，该方法和系统包括提供形成在电介质上的沟槽中的铜互连。 铜互连包括设置在沟槽中的铜层和设置在铜层上方的层。 铜层至少有一颗竹结构。 至少一个颗粒具有基本上一个取向。

公开(公告)号：US08735960B2

公开(公告)日：2014-05-27

申请号：US12313134

申请日：2008-11-17

申请人： Minh Q. Tran ,  Minh-Van Ngo ,  Alexander H. Nickel ,  Sung Jin Kim ,  Simon Chan ,  Ning Cheng

发明人： Minh Q. Tran ,  Minh-Van Ngo ,  Alexander H. Nickel ,  Sung Jin Kim ,  Simon Chan ,  Ning Cheng

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L23/485 ,  H01L29/66825 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.

摘要翻译： 紫外线吸收剂氮氧化硅层覆盖包括一对源极/漏极，栅极绝缘体，浮动栅极，电介质层和控制栅极的存储单元。 导电体通过硅氧氮化物层设置，用于与控制栅极电连接，并且另一个导体通过氧氮化硅层设置，用于电连接到源极/漏极。

公开(公告)号：US08618354B2

公开(公告)日：2013-12-31

申请号：US12898216

申请日：2010-10-05

申请人： Simon Chan ,  Ravi Maruthachalam

发明人： Simon Chan ,  Ravi Maruthachalam

IPC分类号： C12N15/82 ,  A01H5/10 ,  C12N15/29 ,  C12N15/62 ,  C07K14/415 ,  A01H1/08

CPC分类号： A01H1/08 ,  A01H1/02 ,  C07K14/415 ,  C12N15/8241 ,  C12N15/8261 ,  C12N15/8287 ,  Y02A40/146

摘要： Methods and compositions for generating haploid organisms are described.

公开(公告)号：US20050263753A1

公开(公告)日：2005-12-01

申请号：US11179282

申请日：2005-07-12

申请人： Mario Pelella ,  Simon Chan

发明人： Mario Pelella ,  Simon Chan

IPC分类号： C30B25/18 ,  H01L21/20 ,  H01L21/304 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3043 ,  H01L29/7842

摘要： An integrated circuit (IC) utilizes a strained layer. The substrate can utilize trenches in a base layer to induce stress in a layer. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.

摘要翻译： 集成电路（IC）利用应变层。 衬底可以利用基层中的沟槽以在层中诱导应力。 沟槽在绝缘体上半导体（SOI）晶片的体基板或基底层的背侧上限定支柱。

公开(公告)号：US20050158963A1

公开(公告)日：2005-07-21

申请号：US10759207

申请日：2004-01-20

申请人： Darin Chan ,  Simon Chan ,  Angela Hui

发明人： Darin Chan ,  Simon Chan ,  Angela Hui

IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/336

CPC分类号： H01L21/76224

摘要： Planarized STI with minimized topography is formed by selectively etching back the dielectric trench fill with respect to the polish stop film prior to removing the polish stop film. Embodiments include etching back a silicon oxide trench filled to a depth of about 200 Å to about 1,500 Å, and then stripping a silicon nitride polish stop layer leaving a substantially planarized surface, thereby improving the accuracy of subsequent gate electrode patterning and reducing stringers.

摘要翻译： 通过在去除抛光停止膜之前相对于抛光止挡膜选择性地蚀刻回介质沟槽填充物而形成具有最小化形貌的平坦化STI。 实施例包括将填充至大约至大约深度的氧化硅沟槽刻蚀，然后剥离留下基本平坦化表面的氮化硅抛光停止层，从而提高随后的栅电极图案化和减少桁条的精度。