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    Planar voltage contrast test structure
    4.
    发明授权
    Planar voltage contrast test structure 有权
    平面电压对比测试结构

    公开(公告)号：US07902548B2

    公开(公告)日：2011-03-08

    申请号：US11558079

    申请日：2006-11-09

    申请人： Seng-Keong Victor Lim ,  Dennis Tan ,  Tze Ho Simon Chan

    发明人： Seng-Keong Victor Lim ,  Dennis Tan ,  Tze Ho Simon Chan

    IPC分类号： H01L21/00

    CPC分类号： G01R31/307 ,  G01R31/2853 ,  G01R31/2884

    摘要： An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned in the space. Structures for detecting open circuits and short circuits are described.

    摘要翻译： 公开了集成电路和电子束测试方法。 集成电路包括具有接地栅格的测试结构，金属垫在其内具有空间并位于接地格栅内，金属线连接到接地格并定位在该空间中。 描述了用于检测开路和短路的结构。

    PLANAR VOLTAGE CONTRAST TEST STRUCTURE
    5.
    发明申请
    PLANAR VOLTAGE CONTRAST TEST STRUCTURE 有权
    平面电压对比度测试结构

    公开(公告)号：US20070085556A1

    公开(公告)日：2007-04-19

    申请号：US11558079

    申请日：2006-11-09

    申请人： Seng-Keong Victor Lim ,  Dennis Tan ,  Tze Ho Simon Chan

    发明人： Seng-Keong Victor Lim ,  Dennis Tan ,  Tze Ho Simon Chan

    IPC分类号： G01R31/02

    CPC分类号： G01R31/307 ,  G01R31/2853 ,  G01R31/2884

    摘要： An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned in the space. Structures for detecting open circuits and short circuits are described.

    摘要翻译： 公开了集成电路和电子束测试方法。 集成电路包括具有接地栅格的测试结构，金属垫在其内具有空间并位于接地格栅内，金属线连接到接地格并定位在该空间中。 描述了用于检测开路和短路的结构。

    Horizontal tram
    6.
    发明授权
    Horizontal tram 有权
    水平电车

    公开(公告)号：US07183590B2

    公开(公告)日：2007-02-27

    申请号：US11422560

    申请日：2006-06-06

    申请人： Jia Zhen Zheng ,  Weining Li ,  Tze Ho Simon Chan ,  Pradeep Ramachandramurthy Yelehanka

    发明人： Jia Zhen Zheng ,  Weining Li ,  Tze Ho Simon Chan ,  Pradeep Ramachandramurthy Yelehanka

    IPC分类号： H01L29/74

    CPC分类号： H01L27/11 ,  H01L27/0617 ,  H01L29/66393 ,  H01L29/7436

    摘要： An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

    摘要翻译： 集成电路结构包括提供半导体衬底并在其中形成沟槽。 在沟槽周围和半导体衬底内形成晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 晶闸管的栅极形成在沟槽内。 在半导体衬底上形成存取晶体管。 在晶闸管和存取晶体管之间形成互连。

    Method to lower work function of gate electrode through Ge implantation
    7.
    发明授权
    Method to lower work function of gate electrode through Ge implantation 有权
    通过Ge注入来降低栅电极的功函数的方法

    公开(公告)号：US07101746B2

    公开(公告)日：2006-09-05

    申请号：US10701963

    申请日：2003-11-05

    申请人： Tze Ho Simon Chan ,  Mousumi Bhat ,  Jeffrey Chee

    发明人： Tze Ho Simon Chan ,  Mousumi Bhat ,  Jeffrey Chee

    IPC分类号： H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/823842 ,  H01L21/32155 ,  H01L21/82385

    摘要： A method for forming selective P type and N type gates is described. A gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. Germanium ions are implanted into a portion of the polysilicon layer not covered by a mask to form a polysilicon-germanium layer. The polysilicon layer and the polysilicon-germanium layer are patterned to form NMOS polysilicon gates and PMOS polysilicon-germanium gates. In an alternative, nitrogen ions are implanted into the polysilicon-germanium layer and the gates are annealed after patterning to redistribute the germanium ions throughout the polysilicon-germanium layer. In a second alternative, germanium ions are implanted into a first thin polysilicon layer, then a second polysilicon layer is deposited to achieve the total polysilicon layer thickness before patterning the gates.

    摘要翻译： 描述了形成选择性P型和N型栅极的方法。 生长在半导体衬底上的栅氧化层。 沉积在栅极氧化物层上的多晶硅层。 将锗离子注入到未被掩模覆盖的多晶硅层的一部分中以形成多晶硅 - 锗层。 图案化多晶硅层和多晶硅 - 锗层以形成NMOS多晶硅栅极和PMOS多晶硅 - 锗栅极。 替代地，将氮离子注入到多晶硅 - 锗层中，并且在图案化之后对栅极进行退火以将锗离子重新分布在整个多晶硅 - 锗层中。 在第二替代方案中，将锗离子注入到第一薄多晶硅层中，然后沉积第二多晶硅层以在栅极图案化之前实现总多晶硅层厚度。

    Method of forming planarized shallow trench isolation
    9.
    发明申请
    Method of forming planarized shallow trench isolation 审中-公开
    形成平坦化浅沟槽隔离的方法

    公开(公告)号：US20050158963A1

    公开(公告)日：2005-07-21

    申请号：US10759207

    申请日：2004-01-20

    申请人： Darin Chan ,  Simon Chan ,  Angela Hui

    发明人： Darin Chan ,  Simon Chan ,  Angela Hui

    IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/336

    CPC分类号： H01L21/76224

    摘要： Planarized STI with minimized topography is formed by selectively etching back the dielectric trench fill with respect to the polish stop film prior to removing the polish stop film. Embodiments include etching back a silicon oxide trench filled to a depth of about 200 Å to about 1,500 Å, and then stripping a silicon nitride polish stop layer leaving a substantially planarized surface, thereby improving the accuracy of subsequent gate electrode patterning and reducing stringers.

    摘要翻译： 通过在去除抛光停止膜之前相对于抛光止挡膜选择性地蚀刻回介质沟槽填充物而形成具有最小化形貌的平坦化STI。 实施例包括将填充至大约至大约深度的氧化硅沟槽刻蚀，然后剥离留下基本平坦化表面的氮化硅抛光停止层，从而提高随后的栅电极图案化和减少桁条的精度。

    Siliciding spacer in integrated circuit technology
    10.
    发明申请
    Siliciding spacer in integrated circuit technology 审中-公开
    集成电路技术中的硅化间隔器

    公开(公告)号：US20050048731A1

    公开(公告)日：2005-03-03

    申请号：US10654123

    申请日：2003-09-02

    申请人： Jeffrey Patton ,  Mehrdad Mahanpour ,  Thorsten Kammler ,  David Brown ,  Paul Besser ,  Simon Chan ,  Austin Frenkel

    发明人： Jeffrey Patton ,  Mehrdad Mahanpour ,  Thorsten Kammler ,  David Brown ,  Paul Besser ,  Simon Chan ,  Austin Frenkel

    IPC分类号： H01L21/336 ,  H01L21/4763

    CPC分类号： H01L29/665 ,  H01L29/6656 ,  H01L29/6659

    摘要： A method of forming an integrated circuit and a structure therefore is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. Shallow source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate. Deep source/drain junctions are formed in the semiconductor substrate using the sidewall spacer. A siliciding spacer is formed over the sidewall spacer after forming the shallow and deep source/drain junctions. A silicide is formed on the deep source/drain junctions adjacent the siliciding spacer, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the silicide.

    摘要翻译： 因此，提供了形成集成电路和结构的方法。 在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。 在半导体衬底中形成浅源极/漏极结。 在栅极周围形成侧壁间隔物。 使用侧壁间隔物在半导体衬底中形成深源极/漏极结。 在形成浅的和深的源极/漏极结之后，在侧壁间隔物上形成硅化间隔物。 在邻近硅化间隔物的深源极/漏极结上形成硅化物，并且在半导体衬底上沉积电介质层。 然后在电介质层中形成与硅化物的接触。