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公开(公告)号：US20180074951A1
公开(公告)日：2018-03-15
申请号：US15359225
申请日：2016-11-22
Applicant: Pure Storage, Inc.
Inventor： Boris Feigin , Robert Lee , Svitlana Tumanova , Taher Vohra
CPC classification number: G06F12/0246 , G06F3/0605 , G06F3/0647 , G06F3/0652 , G06F3/0688 , G06F2212/7205
Abstract: A method for elective garbage collection in storage memory, performed by a storage system is provided. The method includes monitoring storage space available in each of a plurality of portions of storage memory of a storage system and detecting an imbalance in the storage space available across the plurality of portions of storage memory. The method includes performing garbage collection to rebalance the space available across the plurality of portions of storage memory, responsive to the detecting. A storage system is also provided.
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公开(公告)号：US12236117B2
公开(公告)日：2025-02-25
申请号：US18460269
申请日：2023-09-01
Applicant: PURE STORAGE, INC.
Inventor： Hari Kannan , Gordon James Coleman , Yijie Zhao , Peter E. Kirkpatrick , Robert Lee , Yuhong Mao , Boris Feigin
Abstract: One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.
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公开(公告)号：US12093545B2
公开(公告)日：2024-09-17
申请号：US17570340
申请日：2022-01-06
Applicant: PURE STORAGE, INC.
Inventor： Ying Gao , Boris Feigin , Hari Kannan , Igor Ostrovsky , Jeffrey Tofano , Svitlana Tumanova
IPC: G06F3/06
CPC classification number: G06F3/0634 , G06F3/0614 , G06F3/0679 , G06F3/0689
Abstract: A storage system has a first memory, a second memory that include solid-state storage memory, and a processing device. The processing device is to select a mode for each portion of data to be written. Selection of the mode is based at least on size of the portion of data. Selection of the mode is from among modes that include a first mode of writing the portion of data in mirrored RAID form to the first memory for later transfer from the first memory to the second memory, a second mode of writing the portion of data in parity-based RAID form to the first memory for later transfer from the first memory to the second memory, and a third mode of writing the portion of data to the second memory, bypassing the first memory. The processing device is to handle portions of data to be written according to such selection.
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公开(公告)号：US12067282B2
公开(公告)日：2024-08-20
申请号：US17831339
申请日：2022-06-02
Applicant: PURE STORAGE, INC.
Inventor： Ying Gao , Boris Feigin , Hari Kannan
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes selecting one of a plurality of write paths for incoming data, and writing the incoming data via the selected write path. A first write path includes writing to NVRAM, writing from NVRAM to SLC flash memory and writing from SLC flash memory to QLC flash memory. A second write path includes writing to NVRAM and writing from NVRAM to QLC flash memory, bypassing SLC flash memory. A third write path includes writing to SLC flash memory, bypassing NVRAM, and writing from SLC flash memory to QLC flash memory.
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公开(公告)号：US11947814B2
公开(公告)日：2024-04-02
申请号：US17486084
申请日：2021-09-27
Applicant: PURE STORAGE, INC.
Inventor： Ian Juch , Haijie Xiao , Hao Liu , Boris Feigin
IPC: G06F3/06
CPC classification number: G06F3/0631 , G06F3/0619 , G06F3/0689
Abstract: A storage system determines a change in storage system geometry that affects at least one previously formed resiliency group of storage system resources. The storage system forms at least one resiliency group of storage system resources in accordance with rules that emphasize stability of formation of resiliency groups. The storage system accesses data stripes across storage system resources of resiliency groups.
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Patent Agency Ranking
公开(公告)号：US11886334B2
公开(公告)日：2024-01-30
申请号：US17831295
申请日：2022-06-02
Applicant: Pure Storage, Inc.
Inventor： Hari Kannan , Ying Gao , Boris Feigin
CPC classification number: G06F12/0246 , G06F3/061 , G06F3/0605 , G06F3/0647 , G06F3/0652 , G06F3/0653 , G06F3/0688 , G06F11/3034 , G06F2212/7205
Abstract: A storage system has NVRAM (non-volatile random-access memory), solid-state storage memory, and a processor to perform a method. The method includes allocating virtual units of NVRAM with mapping of the virtual units to physical memory. The method includes writing data having various sizes into allocated first virtual units of memory and into allocated second virtual units of memory. The first virtual units of memory each include a first contiguous physical addressed amount of NVRAM having a first size. The second virtual units of memory each include an amount of NVRAM having a second size. The method includes relocating at least some of the data such that a portion of the allocated second virtual units of memory become available for the allocating.
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公开(公告)号：US11782625B2
公开(公告)日：2023-10-10
申请号：US17379762
申请日：2021-07-19
Applicant: Pure Storage, Inc.
Inventor： Robert Lee , Boris Feigin , Ying Gao , Ronald Karr
CPC classification number: G06F3/0644 , G06F3/0619 , G06F3/0659 , G06F3/0688 , G06F16/119
Abstract: A method of operating a storage system, and related storage system, are provided. The storage system establishes resiliency groups, each having a defined level of redundancy of resources of the storage system. The resiliency groups include at least one compute resources resiliency group and at least one storage resources resiliency group. The storage system supports capability of configurations that have multiples of each of the resiliency groups. Blades of the storage system perform distributed data and metadata storage across modular storage devices, in accordance with the resiliency groups.
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公开(公告)号：US11614880B2
公开(公告)日：2023-03-28
申请号：US17139460
申请日：2020-12-31
Applicant: PURE STORAGE, INC.
Inventor： Ying Gao , Boris Feigin , Hari Kannan , Igor Ostrovsky , Jeffrey Tofano
IPC: G06F3/06
Abstract: A storage system has a first memory, and a second memory that includes storage memory. The storage system has a processing device. The processing device is to select whether to write data to the first memory and write the data from the first memory to the second memory, or to write the data to the second memory bypassing the first memory. The processing device is to write portions of data for storage according to such selection.
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公开(公告)号：US11487455B2
公开(公告)日：2022-11-01
申请号：US17124851
申请日：2020-12-17
Applicant: PURE STORAGE, INC.
Inventor： Hari Kannan , Gordon James Coleman , Yijie Zhao , Peter E. Kirkpatrick , Robert Lee , Yuhong Mao , Boris Feigin
Abstract: One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.
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公开(公告)号：US20220300193A1
公开(公告)日：2022-09-22
申请号：US17831339
申请日：2022-06-02
Applicant: PURE STORAGE, INC.
Inventor： Ying Gao , Boris Feigin , Hari Kannan
IPC: G06F3/06
Abstract: A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes selecting one of a plurality of write paths for incoming data, and writing the incoming data via the selected write path. A first write path includes writing to NVRAM, writing from NVRAM to SLC flash memory and writing from SLC flash memory to QLC flash memory. A second write path includes writing to NVRAM and writing from NVRAM to QLC flash memory, bypassing SLC flash memory. A third write path includes writing to SLC flash memory, bypassing NVRAM, and writing from SLC flash memory to QLC flash memory.
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