公开(公告)号：US09417807B2

公开(公告)日：2016-08-16

申请号：US14820207

申请日：2015-08-06

Applicant: RAMBUS INC.

Inventor： Kambiz Kaviani ,  Amir Amirkhany ,  Dinesh Patil ,  Mohammad Hekmat

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G11C5/04 ,  G11C7/10 ,  G06F12/08

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0683 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/20 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/1093

Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

Abstract translation: 描述了具有基于选通脉冲的主界面和在存储器模块上使用的无频闪次要接口的数据缓冲器。 一个存储器模块包括地址缓冲器，数据缓冲器和多个动态随机存取存储器（DRAM）器件。 地址缓冲器通过无闪光次要接口向数据缓冲器和DRAM器件提供定时参考，用于数据缓冲器和DRAM器件之间的一个或多个事务。

公开(公告)号：US20160041781A1

公开(公告)日：2016-02-11

申请号：US14820207

申请日：2015-08-06

Applicant: RAMBUS INC.

Inventor： Kambiz Kaviani ,  Amir Amirkhany ,  Dinesh Patil ,  Mohammad Hekmat

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0683 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/20 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/1093

Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

Abstract translation: 描述了具有基于选通脉冲的主界面和在存储器模块上使用的无频闪次要接口的数据缓冲器。 一个存储器模块包括地址缓冲器，数据缓冲器和多个动态随机存取存储器（DRAM）器件。 地址缓冲器通过无闪光次要接口向数据缓冲器和DRAM器件提供定时参考，用于数据缓冲器和DRAM器件之间的一个或多个事务。

公开(公告)号：US20150333938A1

公开(公告)日：2015-11-19

申请号：US14720518

申请日：2015-05-22

Applicant: Rambus Inc.

Inventor： Kambiz Kaviani ,  Amir Amirkhany ,  Jason Chia-Jen Wei ,  Aliazam Abbasfar

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04B1/123 ,  H04L25/03063 ,  H04L25/03885

Abstract: A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.

Abstract translation: 校准反馈均衡器以补偿接收信号中的估计符号间干扰和采样设备的偏移。 判定反馈均衡器被配置为使得采样电路的输出信号表示在校准下的输入信号和采样电路的基准之间的比较。 在包括预定图案的通信信道上接收输入信号。 将预定模式与输出信号进行比较，以确定用于配置考虑到偏移和符号间干扰效应两者的采样电路的调整参考。

公开(公告)号：US09158679B2

公开(公告)日：2015-10-13

申请号：US14028172

申请日：2013-09-16

Applicant: RAMBUS INC.

Inventor： Kambiz Kaviani ,  Amir Amirkhany ,  Dinesh Patil ,  Mohammad Hekmat

IPC: G06F12/00 ,  G06F12/02 ,  G11C5/04 ,  G11C7/10

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0683 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/20 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/1093

Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

Abstract translation: 描述了具有基于选通脉冲的主界面和在存储器模块上使用的无频闪次要接口的数据缓冲器。 一个存储器模块包括地址缓冲器，数据缓冲器和多个动态随机存取存储器（DRAM）器件。 地址缓冲器通过无闪光次要接口向数据缓冲器和DRAM器件提供定时参考，用于数据缓冲器和DRAM器件之间的一个或多个事务。

公开(公告)号：US08937994B2

公开(公告)日：2015-01-20

申请号：US13915290

申请日：2013-06-11

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Kambiz Kaviani ,  Aliazam Abbasfar

IPC: H03H7/30 ,  H03K5/24

CPC classification number: H04L25/03949 ,  H03K5/24

Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

Abstract translation: 部分响应判决反馈均衡器（PrDFE）包括至少包括第一和第二比较器的接收器，该第一和第二比较器可操作以将表示符号序列的输入信号与相应阈值进行比较，并且分别产生第一和第二接收器输出。 提供第一选择级，以根据第一定时信号在第一比较器输出和第一解析符号之间选择（a），以及（b）根据第一定时信号在第二比较器输出和第一解析符号之间选择 产生相应的第一和第二选择输出。 第二选择阶段根据选择信号在第一和第二选择输出之间进行选择。 选择信号取决于序列中第一个已解析符号之前的先前解析符号。

公开(公告)号：US20130290766A1

公开(公告)日：2013-10-31

申请号：US13867954

申请日：2013-04-22

Applicant: RAMBUS INC.

Inventor： Huy Nguyen ,  Vijay Gadde ,  Kambiz Kaviani ,  Thomas Giovannini ,  Todd Bystrom

IPC: G06F1/12

CPC classification number: G06F1/12

Abstract: A source-synchronous communication system in which a first integrated circuit (IC) conveys a data signal and concomitant strobe signal to a second IC. One or both ICs support hysteresis for the strobe channel that allows the second IC to distinguish between strobe preambles and noise, and thus prevent the false triggering of data capture. Hysteresis may also be employed to quickly settle the strobe channel to an inactive level after receipt of a strobe postamble.

Abstract translation: 一种源同步通信系统，其中第一集成电路（IC）向第二IC传送数据信号和伴随选通信号。 一个或两个IC支持选通通道的滞后，允许第二IC区分选通前导和噪声，从而防止数据捕获的错误触发。 还可以采用迟滞来在接收到选通后同步码之后快速地将频闪通道置于非活动状态。