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    Folded memory modules
    1.
    发明授权
    Folded memory modules 有权

    公开(公告)号：US12147367B2

    公开(公告)日：2024-11-19

    申请号：US18355660

    申请日：2023-07-20

    Applicant: Rambus Inc.

    Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

    IPC: G06F13/40 ,  G06F12/00 ,  G06F13/00 ,  G06F13/16

    Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

    FOLDED MEMORY MODULES
    2.
    发明申请
    FOLDED MEMORY MODULES 有权

    公开(公告)号：US20210124703A1

    公开(公告)日：2021-04-29

    申请号：US16950861

    申请日：2020-11-17

    Applicant: Rambus Inc.

    Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

    IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

    Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

    Optimizing power in a memory device
    3.
    发明授权
    Optimizing power in a memory device 有权

    公开(公告)号：US10761587B2

    公开(公告)日：2020-09-01

    申请号：US16193247

    申请日：2018-11-16

    Applicant: RAMBUS INC.

    Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

    IPC: G06F1/324 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G06F1/3234 ,  G06F1/3287 ,  G06F5/06 ,  G11C7/04 ,  H03L7/081

    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

    OPTIMIZING POWER IN A MEMORY DEVICE
    6.
    发明申请
    OPTIMIZING POWER IN A MEMORY DEVICE 有权
    优化存储器件中的电源

    公开(公告)号：US20170052584A1

    公开(公告)日：2017-02-23

    申请号：US15248364

    申请日：2016-08-26

    Applicant: RAMBUS INC.

    Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

    IPC: G06F1/32 ,  G11C7/10 ,  G06F5/06 ,  G11C7/22

    CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G06F2205/067 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272 ,  H03L7/0816

    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

    Abstract translation: 实施例通常涉及存储器件。 在一个实施例中，存储器件包括时钟接收器电路，其接收外部时钟信号并提供内部时钟信号。 存储装置还包括具有输入的延迟锁定环路电路（DLL）和接收内部时钟信号的电路。 该电路选择内部时钟信号的哪些脉冲被施加到DLL的输入端，使得从外部时钟信号的至少三个连续脉冲中选出的不超过两个时钟脉冲在预定的时间内被施加到DLL的输入 间隔。 在另一个实施例中，一种方法包括在时钟接收器电路处接收外部时钟信号，从时钟接收器电路接收内部时钟信号，以及选择内部时钟信号的哪些脉冲被施加到DLL的输入，其中不再有 从外部时钟信号的至少三个连续脉冲中选择的两个时钟脉冲在预定间隔期间被施加到DLL的输入端。

    Optimizing power in a memory device
    8.
    发明授权
    Optimizing power in a memory device 有权
    优化存储设备的电源

    公开(公告)号：US09431089B2

    公开(公告)日：2016-08-30

    申请号：US14405910

    申请日：2013-06-10

    Applicant: RAMBUS INC.

    Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

    IPC: G11C8/00 ,  G11C11/4076 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  H03L7/081 ,  G11C7/04

    CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G06F2205/067 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272 ,  H03L7/0816

    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

    Abstract translation: 实施例通常涉及存储器件。 在一个实施例中，存储器件包括时钟接收器电路，其接收外部时钟信号并提供内部时钟信号。 存储装置还包括具有输入的延迟锁定环路电路（DLL）和接收内部时钟信号的电路。 该电路选择内部时钟信号的哪些脉冲被施加到DLL的输入端，使得从外部时钟信号的至少三个连续脉冲中选出的不超过两个时钟脉冲在预定的时间内被施加到DLL的输入 间隔。 在另一个实施例中，一种方法包括在时钟接收器电路处接收外部时钟信号，从时钟接收器电路接收内部时钟信号，以及选择内部时钟信号的哪些脉冲被施加到DLL的输入，其中不再有 从外部时钟信号的至少三个连续脉冲中选择的两个时钟脉冲在预定间隔期间被施加到DLL的输入端。

    Crosstalk reduction coding schemes
    10.
    发明授权
    Crosstalk reduction coding schemes 有权
    串扰减少编码方案

    公开(公告)号：US08964879B2

    公开(公告)日：2015-02-24

    申请号：US13937549

    申请日：2013-07-09

    Applicant: Rambus Inc.

    Inventor： Reza Navid ,  Amir Amirkhany ,  Dinesh D. Patil ,  Brian S. Leibowitz

    IPC: H04B15/00 ,  H04L1/00

    CPC classification number: H04L1/0083 ,  H04L1/0001 ,  H04L1/0002 ,  H04L1/0007

    Abstract: Data coding schemes perform level-based and/or transition-based encoding to avoid signaling conditions that create worst case crosstalk during transmission of multi-bit data from one circuit to another circuit via a parallel communication link. The coding schemes disallow certain patterns from being present in the signal levels, signal transitions, or a combination of the signal levels and signal transitions that occur in a subset of the multi-bit data that corresponds to certain physically neighboring wires of the parallel communication link.

    Abstract translation: 数据编码方案执行基于电平和/或基于转换的编码，以避免在通过并行通信链路将多位数据从一个电路传输到另一电路时产生最差情况串扰的信令条件。 编码方案不允许某些模式存在于信号电平，信号转换或信号电平和信号转换的组合中，信号电平和信号转换发生在对应于并行通信链路的某些物理相邻电线的多位数据的子集中 。

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