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31.发明申请System and Method for Completing Full Updates to Entire Cache Lines Stores with Address-Only Bus Operations 有权完整的完整更新的系统和方法完整的缓存行存储仅地址总线操作公开(公告)号：US20080140943A1
公开(公告)日：2008-06-12
申请号：US12034769
申请日：2008-02-21
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804
摘要： A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.
摘要翻译： 一种方法和处理器系统，其在完成具有完整存储队列条目的整个高速缓存行的更新时基本上消除数据总线操作。 处理器芯片内的存储队列设计有连接相应条目的字节使能位的各个位的一系列与门。 AND输出被馈送到STQ控制器，并在条目已满时发出信号。 当选择完整条目以发送到RC机器时，RC机器发出信号，表示该条目更新整个高速缓存行。 RC机器获得线路的写入权限，然后RC机器覆盖整个高速缓存行。 由于整个高速缓存线被覆盖，当缓存线的请求在高速缓存中丢失或数据在RC写入权限获得之前状态时，不会检索高速缓存行的数据。
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32.发明授权Method, apparatus and system that cache promotion information within a processor separate from instructions and data 有权缓存处理器内的促销信息与指令和数据分离的方法，装置和系统公开(公告)号：US06920514B2
公开(公告)日：2005-07-19
申请号：US10268739
申请日：2002-10-10
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F12/0815
摘要： A data processing system includes a global promotion facility and a plurality of processing units coupled by an interconnect. At least one processing unit among the plurality of processing units includes one or more second caches having cache arrays in which instructions and operand data are cached, an instruction sequencing unit, an execution unit that executes an acquisition instruction to acquire a promotion bit field within the global promotion facility exclusive of at least one other processing unit, and a promotion cache separate from the one or more second caches. In response to acquisition of the promotion bit field by the first processor, the promotion cache of the first processor stores the promotion bit field separately from instructions and operand data.
摘要翻译： 数据处理系统包括全球推广设施和通过互连耦合的多个处理单元。 多个处理单元中的至少一个处理单元包括具有高速缓存阵列的一个或多个第二高速缓冲存储器，其中指令和操作数据被缓存，指令排序单元，执行单元，执行获取指令以获取内部的提升位字段 全球推广设施，不包括至少一个其他处理单元，以及与所述一个或多个第二高速缓存分开的升级缓存。 响应于由第一处理器获取促销位字段，第一处理器的升级缓存存储与指令和操作数数据分开的促销位字段。
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33.发明授权Method and apparatus for transferring data between buses having differing ordering policies via the use of autonomous units 失效用于通过使用自主单元在具有不同排序策略的总线之间传送数据的方法和装置
公开(公告)号：US06016526A
公开(公告)日：2000-01-18
申请号：US934415
申请日：1997-09-19
CPC分类号： G06F13/4013
摘要： A method and apparatus for ordering operations and data received by a first bus having a first ordering policy according to a second ordering policy which is different from the first ordering policy, and for transferring the ordered data to the second bus having the second ordering policy. The apparatus includes at least one first unit for a first class of operations, each first unit being assigned to a single first class operations at a time. The apparatus also includes at least one second unit for a second class of operations, each second unit being assigned to a single second class operation at time. The apparatus also includes intra prioritizing circuitry, for each class of operations, for prioritizing the assigned operations according to the second ordering policy exclusive of the operations stored in the other classes. The system also includes a tainted unit, for each one of the first and second units, for determining which one of the prioritized operations, residing in either the first or second units, can proceed to execution according to the second ordering policy.
摘要翻译： 一种用于对具有根据与第一排序策略不同的第二排序策略的第一排序策略的第一总线接收的操作和数据的方法和装置，以及用于将有序数据传送到具有第二排序策略的第二总线。 该装置包括用于第一类操作的至少一个第一单元，每个第一单元一次分配给单个第一类操作。 该装置还包括用于第二类操作的至少一个第二单元，每个第二单元在时间被分配到单个第二类操作。 该装置还包括对于每个类别的操作的内部优先级电路，用于根据除了存储在其他类中的操作的第二排序策略来优先分配分配的操作。 该系统还包括针对第一和第二单元中的每一个的污染单元，用于确定驻留在第一或第二单元中的优先操作中的哪一个可以根据第二排序策略进行执行。
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34.发明授权Method and apparatus for controlling autonomous units transferring data between buses having different ordering policies 失效用于控制在具有不同排序策略的总线之间传送数据的自主单元的方法和装置
公开(公告)号：US5938753A
公开(公告)日：1999-08-17
申请号：US934414
申请日：1997-09-19
CPC分类号： G06F13/4013
摘要： A method and system for transferring data between buses having different ordering policies via the use of autonomous units capable of being replicated and layered. The autonomous units include a plurality of execution units which are grouped and assigned a class of data operations for each group. Within each group the operations are ordered according to the sequence in which they were received without regards to outstanding operations in other groups. An intra unit is responsible for prioritizing the ordered operations for all groups in accordance with the a selected one of the ordering policies.
摘要翻译： 一种用于通过使用能够复制和分层的自主单元在具有不同排序策略的总线之间传送数据的方法和系统。 自主单元包括多个执行单元，其被分组并分配了用于每个组的一类数据操作。 在每个组内，根据其收到的顺序对操作进行排序，而不考虑其他组中的未完成操作。 内部单元负责根据所选择的排序策略对所有组的排序操作进行优先级排序。
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公开(公告)号：US5937172A
公开(公告)日：1999-08-10
申请号：US839445
申请日：1997-04-14
CPC分类号： G06F12/0897 , G06F12/0893 , G06F13/1694
摘要： Cache and architectural functions within a cache controller are layered and provided with generic interfaces. Layering cache and architectural operations allows the definition of generic interfaces between controller logic and bus interface units within the controller. The generic interfaces are defined by extracting the essence of supported operations into a generic protocol. The interfaces themselves may be pulsed or held interfaces, depending on the character of the operation. Because the controller logic is isolated from the specific protocols required by a processor or bus architecture, the design may be directly transferred to new controllers for different protocols or processors by modifying the bus interface units appropriately.
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36.发明授权Method and apparatus for transferring data between buses having differing ordering policies 失效用于在具有不同排序策略的总线之间传送数据的方法和装置
公开(公告)号：US5901299A
公开(公告)日：1999-05-04
申请号：US934413
申请日：1997-09-19
CPC分类号： G06F13/4013
摘要： A method and apparatus for ordering operations and data received by a first bus having a first ordering policy according to a second ordering policy which is different from the first ordering policy, and for transferring the order data on a second bus having the second ordering policy. The system includes a plurality of execution units for storing operations and executing the transfer of data between the first and second buses, each one of the execution units being assigned to a group which represents a class of operations. The system also includes intra prioritizer for each group, prioritizing the word operations according to the second ordering policy exclusive of the operation stored in the other groups. The apparatus also includes inter prioritizer for determining which one of the prioritized operations can proceed to execute according to the second ordering policy. The inter prioritizer includes combiner for initially allowing both an assigned read and write operation to proceed to attempt to take control over the second bus, but upon detecting via attempt, allowing the assigned read operation to execute prior to the assigned write operation.
摘要翻译： 一种用于对具有根据与第一排序策略不同的第二排序策略的第一排序策略的第一总线接收的操作和数据的方法和装置，以及用于在具有第二排序策略的第二总线上传送订单数据。 该系统包括用于存储操作并执行第一和第二总线之间的数据传送的多个执行单元，每个执行单元被分配给表示一类操作的组。 该系统还包括每个组的内部优先级排序，除了存储在其他组中的操作之外，根据第二排序策略对单词操作进行优先级排序。 所述装置还包括用于根据所述第二排序策略确定所述优先操作中的哪一个可以继续执行的中间优先级。 间隔优先级器包括组合器，用于最初允许分配的读和写操作两者继续尝试对第二总线进行控制，但是经过尝试检测时，允许所分配的读取操作在所分配的写入操作之前执行。
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公开(公告)号：US5895495A
公开(公告)日：1999-04-20
申请号：US815647
申请日：1997-03-13
IPC分类号： G06F9/52 , G06F12/08 , G06F15/16 , G06F15/177 , G06F13/16
CPC分类号： G06F12/0811
摘要： A method of handling load-and-reserve instructions in a multi-processor computer system wherein the processing units have multi-level caches. Symmetric multi-processor (SMP) computers use cache coherency to ensure the same values for a given memory address are provided to all processors in the system. Load-and-reserve instructions used, for example, in quick read-and-write operations, can become unnecessarily complicated. The present invention provides a method of accessing values in the computer's memory by loading the value from the memory device into all of said caches, and sending a reserve bus operation from a higher-level cache to the next lower-level cache only when the value is to be cast out of the higher cache, and thereafter casting out the value from the higher cache after sending the reserve bus operation. This procedure is preferably used for all caches in a multi-level cache architecture, i.e., when the value is to be cast out of any given cache, a reserve bus operation is sent from the given cache to the next lower-level cache (i.e., the adjacent cache which lies closer to the bus), but the reserve bus operation is not sent to all lower caches. Any attempt by any other processing unit in the computer system to write to an address of the memory device which is associated with the value will then be forwarded to all higher-level caches. The marking of the block as reserved is removed in response to any such attempt to write to the address.
摘要翻译： 一种在多处理器计算机系统中处理加载和备用指令的方法，其中所述处理单元具有多级高速缓存。 对称多处理器（SMP）计算机使用高速缓存一致性来确保给定内存地址的相同值提供给系统中的所有处理器。 例如，在快速读写操作中使用的加载和备份指令可能会变得不必要的复杂。 本发明提供了一种通过将来自存储器设备的值加载到所有高速缓存中来访问计算机存储器中的值的方法，并且只有当值从高级高速缓存发送到下级高级缓存时， 将被抛出较高的缓存，然后在发送备用总线操作之后从较高的缓存中输出该值。 该过程优选地用于多级高速缓存架构中的所有高速缓存，即，当该值将从任何给定的高速缓存中抛出时，预留总线操作从给定的高速缓存发送到下一级的高级缓存（即 ，靠近总线的相邻缓存），但是备用总线操作不发送到所有较低的高速缓存。 计算机系统中的任何其他处理单元尝试写入与该值相关联的存储器件的地址然后将被转发到所有更高级别的高速缓存。 响应于写入地址的任何此类尝试，删除块作为保留的标记。
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38.发明授权System and method for completing updates to entire cache lines with address-only bus operations 有权使用仅地址总线操作完成对整个高速缓存行的更新的系统和方法公开(公告)号：US07360021B2
公开(公告)日：2008-04-15
申请号：US10825189
申请日：2004-04-15
IPC分类号： G06F12/12
CPC分类号： G06F12/0897 , G06F12/0804
摘要： A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.
摘要翻译： 一种方法和处理器系统，其在完成具有完整存储队列条目的整个高速缓存行的更新时基本上消除数据总线操作。 处理器芯片内的存储队列设计有连接相应条目的字节使能位的各个位的一系列与门。 AND输出被馈送到STQ控制器，并在条目已满时发出信号。 当选择完整条目以发送到RC机器时，RC机器发出信号，表示该条目更新整个高速缓存行。 RC机器获得线路的写入权限，然后RC机器覆盖整个高速缓存行。 由于整个高速缓存线被覆盖，当缓存线的请求在高速缓存中丢失时或在RC机器获得写入许可之前数据进入状态时，不会检索高速缓存行的数据。
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39.发明授权Method and data processing system for microprocessor communication in a cluster-based multi-processor network 失效基于群集的多处理器网络中微处理器通信的方法和数据处理系统公开(公告)号：US07073004B2
公开(公告)日：2006-07-04
申请号：US10424255
申请日：2003-04-28
IPC分类号： G06F12/00
CPC分类号： G06F9/52 , G06F12/0831
摘要： The address tenure for PCR synchronization operations is redefined to support inclusion of the synchronization data within the address tenure. The bits of a particular field within the address tenure (e.g., the address field) are re-allocated to synchronization data, which is known to be small enough to fit within the unused bits. The address tenure is then broadcasted as a normal address operation and is snooped by all of the processors. The snooping logic is designed to recognize regular/normal address tenures and these modified address tenures and respond to a receipt of a modified address tenure by removing the synchronization data stored therein and updating the corresponding register location of the PCR.
摘要翻译： 重新定义PCR同步操作的地址保留期，以支持在地址保留期内包含同步数据。 地址占有期内的特定字段的位（例如，地址字段）被重新分配给已知足够小以适合未使用位的同步数据。 然后将地址权限作为正常地址操作广播，并被所有处理器窥探。 窥探逻辑被设计为识别常规/正常地址权属和这些修改的地址权属，并且通过去除存储在其中的同步数据并更新PCR的相应寄存器位置来响应修改的地址保有权的接收。
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40.发明授权Method, apparatus and system for allocating and accessing memory-mapped facilities within a data processing system 失效用于在数据处理系统内分配和访问存储器映射设施的方法，装置和系统公开(公告)号：US06829762B2
公开(公告)日：2004-12-07
申请号：US10268746
申请日：2002-10-10
IPC分类号： G06F946
CPC分类号： G06F12/1433 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： Within a data processing system, a pool of facilities are allocated to an operating system, where each facility within the pool of facilities has an associated real address. The operating system allocates from the pool at least one bypass facility to a first process that the first process is permitted to directly access by its associated real address without first obtaining translation of a non-real address. The operating system also allocates from the pool at least one protected facility to a second process that the second process accesses only by translation of a non-real address to obtain the real address associated with the protected facility. Accesses to the facilities are either protected or unprotected based upon the state of a bypass field within a request address.
摘要翻译： 在数据处理系统中，将一组设施分配给操作系统，其中设施池中的每个设施具有相关联的实际地址。 操作系统从池中分配至少一个旁路设施到第一进程，第一进程允许第一进程通过其相关联的实际地址直接访问，而不首先获得非实际地址的转换。 操作系统还从池中分配至少一个受保护的设施到第二进程，第二进程仅通过非真实地址的转换来访问以获得与受保护设施相关联的真实地址。 根据请求地址中的旁路字段的状态，对设施的访问受到保护或不受保护。
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