公开(公告)号：US06174705B1

公开(公告)日：2001-01-16

申请号：US09425665

申请日：1999-10-22

Applicant: Rebecca Greenwood ,  Richard Nicholas

Inventor： Rebecca Greenwood ,  Richard Nicholas

IPC: C12N121

CPC classification number: C07K14/40

Abstract: The invention provides ARO1 polypeptides and DNA (RNA) encoding such ARO1 and a procedure for producing such polypeptides by recombinant techniques. Also provided are methods for utilizing such ARO1 for the treatment of infection, particularly fungal infections. Antagonists against such ARO1 and their use as a therapeutic to treat infections, particularly fungal infections are also provided. Further provided are diagnostic assays for detecting diseases related to the presence of ARO1 nucleic acid sequences and the polypeptides in a host. Also provided are diagnostic assays for detecting polynucleotides encoding arom and for detecting the polypeptide in a host.

Abstract translation: 本发明提供ARO1多肽和编码这种ARO1的DNA（RNA），以及通过重组技术产生此类多肽的方法。 还提供了利用这种ARO1来治疗感染，特别是真菌感染的方法。 还提供了抗这种ARO1的拮抗剂及其作为治疗感染的用途，特别是真菌感染。 还提供了用于检测与宿主中ARO1核酸序列和多肽的存在相关的疾病的诊断测定法。 还提供了用于检测编码芳香和用于在宿主中检测多肽的多核苷酸的诊断测定法。

公开(公告)号：USD696524S1

公开(公告)日：2013-12-31

申请号：US29421742

申请日：2012-09-12

Applicant: Ali Ersan ,  Richard Nicholas ,  John McKeever

Designer： Ali Ersan ,  Richard Nicholas ,  John McKeever

公开(公告)号：US08122223B2

公开(公告)日：2012-02-21

申请号：US12105401

申请日：2008-04-18

Applicant: Jason F. Cantin ,  Richard Nicholas ,  Eric E. Retter ,  Jeffrey A. Stuecheli

Inventor： Jason F. Cantin ,  Richard Nicholas ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC: G06F12/00 ,  G06F9/26 ,  G06F9/34

CPC classification number: G06F12/0862 ,  G06F12/0831 ,  G06F2212/1016 ,  Y02D10/13

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a current requestor tag matches a previous requestor tag. In particular, a first address and a first requester tag may be extracted from a first data request and a finite state machine (FSM) of a memory controller may be selected whose memory region includes the first address. A second requester tag, that identifies a previous requester that attempted to access the memory region association with the selected FSM, may be retrieved from a register associated with the selected FSM and compared to the first requester tag. Speculatively retrieving the data for the first data request from a main memory may be controlled based on results of the comparison of the first requester tag to the second requester tag.

Abstract translation: 访问推测预测器可以基于当前请求者标签是否匹配先前的请求者标签来预测是否对来自主存储器的数据请求的数据进行推测检索。 特别地，可以从第一数据请求中提取第一地址和第一请求者标签，并且可以选择存储器控制器的有限状态机（FSM），其存储器区域包括第一地址。 可以从与所选FSM相关联的寄存器中检索识别尝试访问与选择的FSM的存储器区域关联的先前请求者的第二请求者标签，并与第一请求者标签进行比较。 可以基于第一请求者标签与第二请求者标签的比较的结果来控制从主存储器推测地检索第一数据请求的数据。

公开(公告)号：US08099570B2

公开(公告)日：2012-01-17

申请号：US12035695

申请日：2008-02-22

Applicant: James A. O'Connor ,  Kanwal Bahri ,  Daniel J. Henderson ,  Luis A. Lastras-Montano ,  Warren E. Maule ,  Michael Mueller ,  Naresh Nayar ,  Richard Nicholas ,  Eric E. Retter ,  William J. Starke ,  Michael R. Trombley ,  Kenneth L. Wright

Inventor： James A. O'Connor ,  Kanwal Bahri ,  Daniel J. Henderson ,  Luis A. Lastras-Montano ,  Warren E. Maule ,  Michael Mueller ,  Naresh Nayar ,  Richard Nicholas ,  Eric E. Retter ,  William J. Starke ,  Michael R. Trombley ,  Kenneth L. Wright

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F11/1666 ,  G06F11/1076 ,  G06F11/20 ,  G06F12/0246 ,  G06F2211/1088

Abstract: Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory.

Abstract translation: 为固态设备中的动态选择性存储器镜像提供了方法，系统和计算机程序产品。 保留一定量的内存。 用于在保留的存储器中选择镜像的存储器的部分是动态确定的。 存储器的选定部分包含关键区域。 存储器的选定部分被镜像在保留的存储器中。

公开(公告)号：US07761277B2

公开(公告)日：2010-07-20

申请号：US11531708

申请日：2006-09-14

Applicant: Richard Nicholas

Inventor： Richard Nicholas

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown Boolean state is provided. When the circuit is simulated, one or more initial simulated logic elements are initialized to the unknown Boolean state. The initialized unknown Boolean states are then fed to one or more simulated logic elements and the simulator simulates the handling of the unknown Boolean state by the simulated logic elements. Examples of simulated logic elements include gates and latches, such as flip-flops, inverters, and basic logic gates. The processing results in at least one negative unknown Boolean state. An example of when a negative unknown Boolean state would result would be when the unknown Boolean state is inverted by an inverter. The resulting negative unknown Boolean state is then fed to other simulated logic elements that generate further simulation results based on processing the negative unknown Boolean state.

Abstract translation: 提供了一种用于模拟使用未知布尔状态和负未知布尔状态的电路设计的系统和方法。 当模拟电路时，一个或多个初始仿真逻辑元件被初始化为未知布尔状态。 然后将初始化的未知布尔状态馈送到一个或多个仿真逻辑元件，并且模拟器通过模拟逻辑元件模拟未知布尔状态的处理。 模拟逻辑元件的示例包括门和锁存器，例如触发器，反相器和基本逻辑门。 处理结果至少有一个负的未知布尔状态。 当未知的布尔状态由逆变器反相时，将产生负的未知布尔状态的一个例子。 然后将所得到的负未知布尔状态馈送到其他仿真逻辑元件，该逻辑元件基于处理负未知布尔状态生成进一步的仿真结果。

公开(公告)号：US20090327619A1

公开(公告)日：2009-12-31

申请号：US12105401

申请日：2008-04-18

Applicant: Jason F. Cantin ,  Richard Nicholas ,  Eric E. Retter ,  Jeffrey A. Stuecheli

Inventor： Jason F. Cantin ,  Richard Nicholas ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC: G06F12/00

CPC classification number: G06F12/0862 ,  G06F12/0831 ,  G06F2212/1016 ,  Y02D10/13

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a current requestor tag matches a previous requestor tag. In particular, a first address and a first requester tag may be extracted from a first data request and a finite state machine (FSM) of a memory controller may be selected whose memory region includes the first address. A second requester tag, that identifies a previous requester that attempted to access the memory region association with the selected FSM, may be retrieved from a register associated with the selected FSM and compared to the first requester tag. Speculatively retrieving the data for the first data request from a main memory may be controlled based on results of the comparison of the first requester tag to the second requester tag.

Abstract translation: 访问推测预测器可以基于当前请求者标签是否匹配先前的请求者标签来预测是否对来自主存储器的数据请求的数据进行推测检索。 特别地，可以从第一数据请求中提取第一地址和第一请求者标签，并且可以选择存储器控制器的有限状态机（FSM），其存储器区域包括第一地址。 可以从与所选FSM相关联的寄存器中检索识别尝试访问与选择的FSM的存储器区域关联的先前请求者的第二请求者标签，并与第一请求者标签进行比较。 可以基于第一请求者标签与第二请求者标签的比较的结果来控制从主存储器推测地检索第一数据请求的数据。

公开(公告)号：US07620749B2

公开(公告)日：2009-11-17

申请号：US11621789

申请日：2007-01-10

Applicant: Giora Biran ,  Luis E. De la Torre ,  Bernard C. Drerup ,  Jyoti Gupta ,  Richard Nicholas

Inventor： Giora Biran ,  Luis E. De la Torre ,  Bernard C. Drerup ,  Jyoti Gupta ,  Richard Nicholas

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A DMA device prefetches descriptors into a descriptor prefetch buffer. The size of descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment. To support a linked list of descriptors, the DMA engine prefetches descriptors based on the assumption that they are sequential in memory and discards any descriptors that are found to violate this assumption. The DMA engine seeks to keep the descriptor prefetch buffer full by requesting multiple descriptors per transaction whenever possible. The bus engine fetches these descriptors from system memory and writes them to the prefetch buffer. The DMA engine may also use an aggressive prefetch where the bus engine requests the maximum number of descriptors that the buffer will support whenever there is any space in the descriptor prefetch buffer. The DMA device discards any remaining descriptors that cannot be stored.

Abstract translation: DMA设备将描述符预取到描述符预取缓冲区中。 描述符预取缓冲区的大小在给定的等待时间环境中保存适当数量的描述符。 为了支持描述符的链表，DMA引擎基于它们在存储器中是连续的假设来预取描述符，并丢弃任何被发现违反这个假设的描述符。 DMA引擎寻求通过每个事务请求多个描述符尽可能地保持描述符预取缓冲区已满。 总线引擎从系统内存中读取这些描述符，并将它们写入预取缓冲区。 DMA引擎还可以使用积极的预取，其中总线引擎请求缓冲区将在描述符预取缓冲器中存在任何空间时将支持的最大数量的描述符。 DMA设备丢弃任何其他不能存储的描述符。

公开(公告)号：US20090265293A1

公开(公告)日：2009-10-22

申请号：US12105427

申请日：2008-04-18

Applicant: Richard Nicholas ,  Ram Raghavan ,  Eric E. Retter ,  Jeffrey A. Stuecheli

Inventor： Richard Nicholas ,  Ram Raghavan ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC: G06N5/00

CPC classification number: G06F12/0862 ,  G06F12/0831 ,  G06F2212/507 ,  G06F2212/6022 ,  G06F2212/6024 ,  Y02D10/13

Abstract: An access speculation predictor is provided that may be implemented using idle command processing resources, such as registers of idle finite state machines (FSMs) in a memory controller. The access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory of the data processing system based on history information stored for a memory region targeted by the data request. In particular, a first address may be extracted from the data request and compared to memory regions associated with second addresses stored in address registers of a plurality of FSMs of the memory controller. A FSM whose memory region includes the first address may be selected. History information for the memory region may be obtained from the selected FSM. The history information may be used to control whether to speculatively retrieve the data for the data request from a main memory.

Abstract translation: 提供了可以使用诸如存储器控制器中的空闲有限状态机（FSM）的寄存器的空闲命令处理资源来实现的访问推测预测器。 访问推测预测器可以基于针对数据请求所针对的存储区域存储的历史信息来预测是否对数据处理系统的主存储器执行针对数据请求的数据的推测检索。 特别地，可以从数据请求中提取第一地址，并与存储在存储器控制器的多个FSM的地址寄存器中的第二地址相关联的存储器区域进行比较。 可以选择其存储区域包括第一地址的FSM。 可以从所选择的FSM获得用于存储器区域的历史信息。 历史信息可以用于控制是否从主存储器推测性地检索数据请求的数据。

公开(公告)号：US20090164736A1

公开(公告)日：2009-06-25

申请号：US11959804

申请日：2007-12-19

Applicant: Robert John Dorsey ,  Jason Alan Cox ,  Hien Minh Le ,  Richard Nicholas ,  Eric Francis Robinson ,  Thuong Quang Truong

Inventor： Robert John Dorsey ,  Jason Alan Cox ,  Hien Minh Le ,  Richard Nicholas ,  Eric Francis Robinson ,  Thuong Quang Truong

IPC: G06F12/08

CPC classification number: G06F12/127 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/128

Abstract: A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block.

Abstract translation: 用于管理高速缓存的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作。 第一PU确定第一PU的第一高速缓存中的多条高速缓存线之一必须被第一数据块替换，并且确定第一数据块是否是来自多个PU中的另一个的受害缓存行。 在第一数据块不是来自多个PU中的另一个的第一数据块的情况下，第一高速缓存不包含一致性状态的高速缓存行无效，并且第一高速缓存包含移动的一致性状态的高速缓存行， 第一PU选择移动的一致性状态的高速缓存行，将第一数据块存储在所选择的高速缓存行中，并更新第一数据块的一致性状态。

公开(公告)号：US20080168191A1

公开(公告)日：2008-07-10

申请号：US11621776

申请日：2007-01-10

Applicant: Giora Biran ,  Luis E. De la Torre ,  Bernard C. Drerup ,  Jyoti Gupta ,  Richard Nicholas

Inventor： Giora Biran ,  Luis E. De la Torre ,  Bernard C. Drerup ,  Jyoti Gupta ,  Richard Nicholas

IPC: G06F13/28 ,  G06F12/14

CPC classification number: G06F13/28

Abstract: A direct memory access (DMA) device includes a barrier and interrupt mechanism that allows interrupt and mailbox operations to occur in such a way that ensures correct operation, but still allows for high performance out-of-order data moves to occur whenever possible. Certain descriptors are defined to be “barrier descriptors.” When the DMA device encounters a barrier descriptor, it ensures that all of the previous descriptors complete before the barrier descriptor completes. The DMA device further ensures that any interrupt generated by a barrier descriptor will not assert until the data move associated with the barrier descriptor completes. The DMA controller only permits interrupts to be generated by barrier descriptors. The barrier descriptor concept also allows software to embed mailbox completion messages into the scatter/gather linked list of descriptors.

Abstract translation: 直接存储器访问（DMA）设备包括屏障和中断机制，允许中断和邮箱操作以确保正确操作的方式发生，但仍然允许在可能的情况下发生高性能无序数据移动。 某些描述符被定义为“屏障描述符”。 当DMA设备遇到屏障描述符时，它确保所有先前的描述符在屏障描述符完成之前完成。 DMA设备进一步确保在与屏障描述符关联的数据移动完成之前，屏障描述符产生的任何中断都不会断言。 DMA控制器仅允许由屏障描述符生成中断。 屏障描述符概念还允许软件将邮箱完成消息嵌入到描述符的分散/收集链接列表中。